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What are the two independent mechanisms for controlling interrupt request?
At the device end, an interrupt enable bit in a control register verifies whether the device is permitted to generate an interrupt request At the processor end, either an interrupt enable nit in the PS or a priority structure verifies whether a given interrupt request will be accepted.
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Q. Perform on occurrence of an interrupt? Determining these requirements let's work out steps that CPU should perform on occurrence of an interrupt. The CPU should find
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