What is glitch? What causes this (describe with waveform)? How to overcome this?

The gated clock‘s corresponding timing diagram demonstrates that it implementation can lead to clock glitches that can cause flip-flop to clock at the wrong time as:

                           a. Gated clock and                              b. Corresponding timing diagram

The above figure demonstrates a synchronous alternative to the gated clock by using a data path. The flip-flop is clocked at each clock cycle and the data path is controlled through an enable. While the enable is Low, the multiplexer feeds the output of the register back onto itself. While the enable is high, then new data is fed to the flip-flop and the register varies its state:

          a. Feedback path and           b. Corresponding timing diagram