Write a control word for counter 1 of 8253 / 8254 that selects the following options:  load least significant byte only, mode 5 of operation and binary counting.  Then write an instruction sequence that will load the control word into 8253 / 8254 that is located at address 01000 h of memory address space. Assume that 8253 / 8254 is attached to the I/O bus of the CPU and the address inputs A0 and A1 are supplied by A2 and A3 respectively.

Ans:

8253/54 Word Format

Depends on the above specified conditions and assuming counter 0 is utilized. The word becomes 0001 1010h.

Know the port address

- The CS is enabled while A7=1

- The Control Register is selected while A1 and A0 =1

- Assuming unemployed address lines A6 to A2 are at logic 0, 

Then port address will be as given below

 Control Register = 83H

 Counter 2 = 82H

 MVI A,B0H

 OUT 83H

 MVI A, LOWBYTE

 OUT 82H

 MVI A,HIGHBYTE

 OUT 82H

LOOP:MVI A,80H

 OUT 83H

 IN 82H

 MOV D,A

 IN 82H

 ORA D

 JNZ LOOP

 RET