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Demonstrate how a typical DMA controller can be interfaced to an 8086/8085 based maximum mode system.
For 8088 in maximum mode:
The RQ/GT0 and RQ/GT1 pins are used to issue DMA request and receive acknowledge signals. Sequence of events of a typical DMA process
1) Peripheral asserts one of the request pins for example RQ/GT1 or RQ/GT0 (RQ/GT0 has higher priority)
2) 8088 completes its current bus cycle and enters into a HOLD state
3) 8088 grants the right of bus control by asserting a grant signal via the same pin as request signal.
4) DMA operation starts
5) Upon completion of the DMA operation, peripheral asserts the request/grant pin again to relinquish bus control.
time to left (TTL) in transport layer
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