Design a mod-12 synchronous up counter, Computer Engineering

Assignment Help:

Design a mod-12 Synchronous up counter.

Ans. Design of a mod 12 synchronous counter by using D-flipflops.

I state table
Present state                                   Next state                                         Required D Inputs

A

B

C

D

A

B

C

D

DA

DB

DC

DD

0

0

0

0

0

0

0

1

0

0

0

1

0

0

0

1

0

0

1

0

0

0

1

0

0

0

1

0

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

0

0

1

0

0

0

1

0

0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

1

0

1

1

1

0

1

1

1

1

0

0

0

1

0

0

0

1

0

0

0

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1

1

0

1

1

1

0

1

1

0

1

0

0

0

1

0

0

Firstly draw the state table containing present state, subsequent state and required flip-flop input to provide the transition. D flip flop offers the output similar as the next state itself. After that, solve through using K maps to determine DA DB DC DD for all states.
Unutilized states are 1100,1101,1110,1111 they can be function as don't care conditions from the table.  Depict  Karnaugh-maps  for  DA,  DB,  DC   and  DD   as  follows  and  acquire  Boolean expressions for them.

355_Design a mod-12 Synchronous up counter.png

569_Design a mod-12 Synchronous up counter12.png

2281_Design a mod-12 Synchronous up counter21.png


Related Discussions:- Design a mod-12 synchronous up counter

Elaborate the various steps in performing a mail merge, COMPUTER FUNDAMENTA...

COMPUTER FUNDAMENTALS 1. Elaborate the various steps in performing a Mail Merge. Perform one mail merge operation for sending invitation for a conference which is being conduc

Advantages offered by data mining, Advantages offered by Data Mining: 1...

Advantages offered by Data Mining: 1.  Facilitates discovery of knowledge from big, massive data sets. 2.  Can be used within dissimilar application areas by Fraud detection

Flip flop., the counter shown Q2Q1Q0=000 The status of Q2Q1Q0 after the pul...

the counter shown Q2Q1Q0=000 The status of Q2Q1Q0 after the pulse

Design a 4:1 mux in verilog, Design a 4:1 mux in Verilog   Mult...

Design a 4:1 mux in Verilog   Multiple styles of coding. e.g. Using if-else statements if(sel_1 == 0 && sel_0 == 0) output = I0; else if(sel_1 == 0 && sel_0 ==

Conversion of decimal number 25.5 into binary number, Conversion of decimal...

Conversion of decimal number 25.5 into binary number Ans. There is integer part is 25 and fractional part is 0.5.  Firstly convert the integer part 25 in its equal to binary numb

Temporary registers w and z, Why the temporary registers W and Z are named ...

Why the temporary registers W and Z are named so I mean we start from A,B,C,D,E then H and L coz H stands for higher bit nd L for lower bit of the address pointed by memory pointer

Regular expression pattern in a wsdl document, Probelm: (a) Show the at...

Probelm: (a) Show the attributes used by Regular Expression Pattern in a WSDL document. (b) Describe the three standard wire formats for transmitting Web Service requests a

Drag and drop state numbers and functions in vb, State 0 Source control is ...

State 0 Source control is being dragged with the variety of a target. 1 Out of the variety of a target. 2 One position in the target to one another.

ERP, ERP usage in real world

ERP usage in real world

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd