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Q. Fundamental differences between RISC and CISC architecture?
Fundamental differences between RISC and CISC architecture. The following table lists following differences:
CISC
RISC
1. Large number of instructions - from
120 to 350.
1. Relatively fewer instructions - less than 100.
2. Employs a variety of data types and a large number of addressing modes.
2. Relatively fewer addressing modes.
3. Variable-length instruction formats.
3. Fixed-length instructions generally 32 bits, easy to decode instruction format.
4. Instructions manipulate operands residing in memory.
4. Mostly register-register operations. The only memory access is by explicit LOAD/STORE instructions.
5. Number of Cycles Per Instruction (CPI) varies from 1-20 depending upon the instruction.
5. Number of CPI is one as it uses pipelining. Pipeline in RISC is optimised due to simple instructions and instruction formats.
6. GPRs varies from 8-32. But no support is available for the parameter passing and function calls.
6. Large number of GPRs are available which are mainly used as Global registers and as a register based procedural call and parameter passing stack so optimised for structured programming.
7. Microprogrammed Control Unit.
7. Hardwired Control Unit.
Let us review the operation of the stack within the 68HC11, the stack is a defined area of RAM which is last in first out register (LIFO) . Access to the stack is made via a stack
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