Explain the asynchronous decade counter, Electrical Engineering

Assignment Help:

Explain the Asynchronous Decade Counter?

The binary counters earlier introduced have two to the power n states. But the counters with states less than this number are as well possible. They are designed to have the number of states in their sequences, which are called as a truncated sequence and these sequences are achieved by forcing the counter to recycle before going through all of its normal states.

A common modulus for the counters with truncated sequences is ten and a counter with ten states in its sequence is called as a decade counter.
By terminate the "ripple-through" counting when the count reaches decimal 9 (binary 1001). ever since the next toggle would set the two most significant bits a NAND gate tied from those two outputs to the asynchronous clear line will start the count over after 9.

1761_Asynchronous Decade Counter.png


Formerly the counter counts to ten (1010) all the flip-flops are being cleared. Notice that the only Q1 and Q3 are used to decode the count of ten. This is called as partial decoding as none of the other states (zero to nine) have both Q1 and Q3 HIGH at the same time.
The sequence of the decade counter is shown in the table below:

235_Asynchronous Decade Counter 1.png


Related Discussions:- Explain the asynchronous decade counter

Define memory for a digital computer, Q. Define Memory For a digital comput...

Q. Define Memory For a digital computer? For a digital computer which stores both programs and data, memory can be divided into three types: random-access memory, mass storage,

Explain extrinsic semiconductor, Explain Extrinsic Semiconductor. Extr...

Explain Extrinsic Semiconductor. Extrinsic Semiconductor: An intrinsic semiconductor is able to conduct some current even at room temperature but as this is not helpful for t

Can you explain about slew rate, Q. Can you explain about Slew Rate? Sl...

Q. Can you explain about Slew Rate? Slew (or slewing) rate is a measure of how fast the output voltage can change. It is given by the maximum value of dvo/dt , which is normall

Block diagram of a 4-bit shift-right register using jkffs, Q. A shift regis...

Q. A shift register can be used as a binary (a) divide- by-2, and (b) multiply-by-2 counter. Explain. Q. Show a block diagram of a 4-bit shift-right register using JKFFs.

Hamming window and zero padding, This question investigates the effect of e...

This question investigates the effect of extending the data set with zero-padding & of the appropriate time in the workflow to apply a window function. To get finer resolution in t

Diode circuits, Diode Circuits: Prob. (a) Draw the piecewise linear v...

Diode Circuits: Prob. (a) Draw the piecewise linear volt ampere characteristic of a p n diode. What are the circuit models for the ON state and the OFF state. (b) Determ

Decoder - introduction to microprocessors , Decoder A decoder is  logic...

Decoder A decoder is  logic  circuit  that energizes a particular  output line for each  combination of input  signal. Fig   shown  the block  diagram  logic diagram  and fu

Characteristics of unijunction transistor, Characteristics of  unijunction...

Characteristics of  unijunction transistor: Characteristics : The static emitter characteristic of UJT at a given inter base voltage VBB in shown in fig. From fig., it is no

Current through each resistor for the networking, Find the current through ...

Find the current through each resistor for the networking below using Mesh Analysis and Nodal Analysis.

Which Transistor configuration best to use in cascade, Q. Which of the 3 tr...

Q. Which of the 3 transistor configuration is best to use in cascade if maximum voltage gain is to be realized?  The common collector configuration is not used for intermediate

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd