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What do you understand by DRAM and its refreshing?
Dynamic RAM (DRAM) is fundamentally the same as SRAM, but this retains data for only 2 or 4 ms on an internal capacitor. But after 2 or 4 ms, the contents of the DRAM should be fully rewritten (refreshed) since the capacitors that is store logic 1 or logic 0, lose their charges. The whole content of the memory is refreshed with 256 reads in a 2-to-4 ms interval. Also refreshing occurs throughout a write, a read or a particular refresh cycle.
a rectangular surge of 2us duration and magnitude of 100Kv travels along a line of surge impedance 500 ohms. The latter is connected to another line of equal impedance through an i
Q. Two wattmeters are used, as shown in Figure, to measure the power absorbed by a balanced delta-connected load. Determine the total power in kW, the power factor, and the per-pha
Considering the TTL NAND gate circuit of Figure, with one or more inputs low, show that the output will be high.
Astigmation control: In most modern oscilloscopes there is an additional focusing control marked Astigmation . This is used to correct an effect which exactly is analogous to
what ''s part of dcmotor or dc generator
Q. Adiodewith the i-v characteristic shown in Figure is used in series with a voltage source of 5 V (forward bias) and a load resistance of 1 k. (a) Determine the current and t
LDAX Load Accumulator Indirect Instruction This instruction is used to copy data from memory location pointed by register pair only BC or DE to the accumulator HL pair
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Q. A four-pole, lap-wound armature has 144 slots with two coil sides per slot, each coil having two turns. If the flux per pole is 20 mWb and the armature rotates at 720 r/min, cal
A 6 V / 2.5 mA relay is connected in the output stage of a transistor. The coil is made of aluminium having α = 0.004. The resistance of the coil is 600 ? at 32 o C. Calculate th
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