Pin functions for the minimum mode operation of 8086 are following:
1) M/I/O -Memory/IO: This is a status line logically equivalent to S2 in maximum mode. When it is low, it denotesthe CPU is having an I/O operation, and when it is high, it denotes that the CPU is having a memory operation. In the previous T4this line becomes active and remains active till last T4 of the current cycle. During local bus this is tristated "hold acknowledge".
2) INTA-interrupt Acknowledge: This signal is utilized as a read strobe for interrupt acknowledge cycles. In other terms, when it goes low, this means that the processor has accepted the interrupt. It is active low during T3, T2 and Tw of each interrupt acknowledge cycle.
3) ALE-Address Latch Enable: This output signal indicates the availability of the valid address on the address/data lines, and is associated to latch enable input of latches. This signal is active high and is never tristated.
4) DT/R -Data Transmit/Receive: This output is utilized to decide the direction of data flow through the transreceivers (bidirectional buffers). When the processor sends data, this signal is high and when the processor is receiving data, this signal is low. Logically, this is corresponding toS1 inmaximum mode. Its timing is the similar as M/I/O. This is tri stated during 'hold acknowledge'.
5) DEN-Data Enable: This signal denote the availability of valid data over the address/data lines. It is utilized to enable the Trans receivers (bidirectional buffers) to separate the data from the multiplexed address/data signal. It is active from the centre of T2 until the middle of T4.
DEN is tristated during 'hold acknowledge' cycle. HLDA-Hold/Holdand HOLD Acknowledge: When the HOLD line go high, it denote to the processor that another master is requesting the bus access. , in the middle of the next clock cycle after receiving the HOLD request the processor is use the hold acknowledge signal on HLDA pin after completing the current bus (instruction) cycle. At the same time, the processor floats the control lines andlocal bus. When the processor detects the HOLD line low then it lowers the HLDA signal. HOLD is asynchronous input and it should be synchronized externally.