Why is Translation Look-aside Buffers (TLBs) important?

The implementation of page-table is completed in the following manner:

• Page table is maintained in main memory.
• PTBR that is Page-table base register points to the page table.
• Page-table length register (PRLR) specifies size of the page table.
• In this system every data or instruction access needs two memory accesses. One for the data or instruction, and one for the page table

The two-memory access problem can be solved through the utilization of a special fast-lookup hardware cache termed as translation look-aside buffers (TLBs) or associative memory. A set of associative registers is made of high-speed memory; here each register contains two parts: a key and a value. While the associative registers are presented along with an item, this is compared with all keys concurrently. If the item is determined, the consequent value field is the output.