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Thread Dump: When we trigger a thread dump on an application server, all active thread informations will be deserted into file which is called as thread dump. Here, we can get information about thread like active thread, hung thread, dead lock, runnable and inactive thread info.
Command: kill -3 PID (Process Id)
Heap Dump: its snap shot of our JVM's heap memory, so here we can have all active java objects and their activities which object actioning what and how much memory it is occupy.
What is branch instruction? As a result of branch instruction is a type of instruction which loads a latest values into the program counter.
Which TTL logic gate is used for wired ANDing ? Ans. Open collector output, TTL logic gate is used.
Unification Algorithm: Here if notice for instance that to unify two sentences as we must find a substitution that makes the two sentences the same. Furthermore remember there
Q. Convert the following BINARY numbers into HEXADECIMAL, double check by converting the result HEXADECIMAL to BINARY. a) 1101.0110 b) 1011.11010 c) 11110.01011
What is recursion? A recursive procedure should have two properties. What are they? Recursion means function call itself repeatedly. Properties : (1) There
Consider that a list of record or a table is stored in the memory and you wish to find some information in that particular list. E.g. the list comprises three fields as displayed b
How numbering plan is achieved in modern telephony? Give the structure with example. The objective of numbering plan is to uniquely identify every subscriber connected to a tel
Explain Hybrid Network in Standard Telephone hand set. Hybrid network: The hybrid network (sometimes termed as a duplex coil or hybrid coil) in a telephone set is a particula
What are the Advantages of carrying out simulations - saves cost (instead of doing the real thing) - Safer (scenarios tried out on the simulation first before used in real
PCI bus transactions: PCI bus traffic is prepared of a series of PCI bus transactions. Each transaction is build up of an address phase that is followed by 1 or more data phas
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