Q. What happens when a negative bias is applied to the gate of a FET?

The result of applying a negative bias to the gate is to reach the saturation level at a lower level of V_DS where V_DS is the voltage between the source and the drain. The resulting saturation value for ID has been reduced and it will continue to decrease as V_GS becomes more and more negative. The pinch off voltage continues to drop in a parabolic manner as V_GS becomes more and more negative. Eventually, V_GS when V_GS = -V_P will be sufficiently negative to establish a saturation level and for all practical purposes the device has been "turned off".