User Account

All Pages

Vhdl, Electrical Engineering

Assignment Help:
Im doing my final year project and Im stuck in vhdl coding. The main mission of this project is to design and build a tap changer which is going to be fitted to power transformers for regulation of the output voltage to required levels for the Micro Grid.
The tap changer system will consist of 9 changers with a 4v step having 9 switches/ Relays. 5 relays will be in the first stage, second stage consist of 3 relays, third stage has got 2 relays and the final stage has 1 relay. The voltage range of the tap changer 399- 431, Tap changer will perform step-up or step-down duties depending on what is requires. ( Tap1-399volts, Tap2 403volts, Tap3 407volts, Tap4 411volts, Tap5 415volts, Tap6 419volts, Tap7 423volts, Tap8 427volts, Tap9 2311volts. )
Im using vhdl programme to control the switches( switch1 to switch 9) using Spartan 3 board and displaying the selected switch on the board. I have written a bit of the the code which is at the bottom and im completely stuck I just need help in finishing the code and have attached the You are my last hope .

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity UPDOWNCOUNTERHOLD is
Port ( Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
-- Automatic : in STD_LOGIC;--- AUTOMATIC SELECTION
Tap_set : in STD_LOGIC;--- ACTIVATES THE TAP SELECTED
SW : in STD_LOGIC_VECTOR (8 downto 0);---- switch for Tap 1 up to 9
--SSG_input : in std_logic_vector(3 downto 0); -- input to seven segment display
Tap_Output: out STD_LOGIC_VECTOR (8 downto 0);-- Tap output
SSG_out : out STD_LOGIC_VECTOR (6 downto 0);--- SEVEN SEGMENT OUTPUT DISPLAY
AN0 : out STD_LoGIC);
end UPDOWNCOUNTERHOLD;

architecture Behavioral of UPDOWNCOUNTERHOLD is

Constant Max_tap :integer := 9;-- referance for the switches
signal Max_tap_vector:std_logic_vector(3 downto 0);
Signal Auto :STD_LOGIC;---- signal for Automatic
Signal Tap_select :STD_LOGIC;-----signal for Tap_set
Signal Switch :std_logic_vector(3 downto 0);----- signal for SW
Signal Tap_out :std_logic_vector(3 downto 0);----- signal for Tap_Output
Signal Seven_segment :std_logic_vector(6 downto 0);----- signal for the seven segment display
SIGNAL S_SW :std_logic_vector(3 DOWNTO 0);----- SIGANAL FOR SWITCH IN MAUNAL/TAP SELECT
BEGIN
PROCESS(Clock,Reset,Tap_set)

BEGIN

IF (Reset = ''1'') THEN

Tap_out <= "0001"; -- reset to tap 1
Seven_segment <= "1001111" ;-- reset it to display tap 1

ELSIF (rising_edge(Clock)) THEN

IF (Tap_set = ''1'') THEN

Tap_Out<= Switch; -- running on manual output depends on the tap switch which is on

end if;

IF (Tap_out > Max_tap) THEN ---- If the output is more than 9 reset

Tap_Out<= "0001"; --- reset to tap 1
Seven_segment <= "1001111" ;-- reset it to display tap 1

IF (conv_integer(Max_tap)) = Max_tap_vector then

--IF (conv_integer(Max_tap_vector)) = Max_tap then------converting interger
--OTHER_VECTOR<=(others =>''0'');
END IF;
END IF;
End if;
END PROCESS;
PROCESS(SW,Clock)
Begin
--S_SW <= SW(3 DOWNTO 0) ;
case SW is
when "0001"=>SSG_out<= "1001111";
when "0010"=>SSG_out<= "0010010";
when "0011"=>SSG_out<= "0000110";
when "0100"=>SSG_out<= "1001100";
when "0101"=>SSG_out<= "0100100";
when "0110"=>SSG_out<= "0100000";
when "0111"=>SSG_out<= "0001111";
when "1000"=>SSG_out<= "0000000";
when "1001"=>SSG_out<= "0000100";
--nothing is displayed when a number more than 9 is given as input.
when others =>SSG_out<="1111111" ;
end case ;
END PROCESS;
end Behavioral;
?

Related Discussions:- Vhdl

Vhdl, Im doing my final year project and Im stuck in vhdl coding. The main...

Im doing my final year project and Im stuck in vhdl coding. The main mission of this project is to design and build a tap changer which is going to be fitted to power transformers

Instruction set architecture, assume that the top of the stack in the progr...

assume that the top of the stack in the program is pointed by the register sp.

Describe two ways of correcting the blur, Q. We have discussed three differ...

Q. We have discussed three different color spaces: RGB, HSI and CMY(K). Specify the need for multiple color spaces. Why can we not use only one? Q. A telescope in an observatory

Power system analysis , how to find z bus matrix

how to find z bus matrix

What do mean by flow of electron, Flow of electrons - Electrons flow down a...

Flow of electrons - Electrons flow down a wire that is what current, is. Good conductors like copper and silver and aluminum have free electrons in their outer shells, and they jum

Balanced score card or bsc, Balanced Score Card or BSC We see in which...

Balanced Score Card or BSC We see in which the traditional model does not reflect the significance of intangible assets, their capturing and measuring mechanism and does not r

Compute the current supplied by the source, Q. A balanced three-phase, wye-...

Q. A balanced three-phase, wye-connected, 2400- V, 60-Hz source supplies two balanced wye- connected loads in parallel. The first draws 15 kVA at 0.8 power factor lagging, and the

How many interrupts does 8085 have, How many interrupts does 8085 have, men...

How many interrupts does 8085 have, mention them The 8085 has 5 interrupt signals; they are INTR, RST7.5, RST6.5, RST5.5 and TRAP

Discuss need of caches, Discuss need of Caches. Caches are other big t...

Discuss need of Caches. Caches are other big thing done in the last 2 decades to enhance performance. Keep things locally when they are going to be used soon. By a physics vie

Electrical drives and actuators, 'Electric drives' is a term used to descri...

'Electric drives' is a term used to describe DC and AC electric motors that provide continuous rotarmotion. They are often controlled by 'electronic drivesystems' designed to contr

Write Your Message!

Captcha
Order Assignment

Featured Services

Order Now

Popular Subjects

Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

Submit Assignment

Academics

Major Subjects

Majors

Get In Touch

whatsapp: +1-415-670-9521

Phone: +1-415-670-9521

Email: [email protected]

TERMS & POLICIES

HELP & SUPPORT

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd