User Account

All Pages

Vhdl, Electrical Engineering

Assignment Help:
Im doing my final year project and Im stuck in vhdl coding. The main mission of this project is to design and build a tap changer which is going to be fitted to power transformers for regulation of the output voltage to required levels for the Micro Grid.
The tap changer system will consist of 9 changers with a 4v step having 9 switches/ Relays. 5 relays will be in the first stage, second stage consist of 3 relays, third stage has got 2 relays and the final stage has 1 relay. The voltage range of the tap changer 399- 431, Tap changer will perform step-up or step-down duties depending on what is requires. ( Tap1-399volts, Tap2 403volts, Tap3 407volts, Tap4 411volts, Tap5 415volts, Tap6 419volts, Tap7 423volts, Tap8 427volts, Tap9 2311volts. )
Im using vhdl programme to control the switches( switch1 to switch 9) using Spartan 3 board and displaying the selected switch on the board. I have written a bit of the the code which is at the bottom and im completely stuck I just need help in finishing the code and have attached the You are my last hope .

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity UPDOWNCOUNTERHOLD is
Port ( Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
-- Automatic : in STD_LOGIC;--- AUTOMATIC SELECTION
Tap_set : in STD_LOGIC;--- ACTIVATES THE TAP SELECTED
SW : in STD_LOGIC_VECTOR (8 downto 0);---- switch for Tap 1 up to 9
--SSG_input : in std_logic_vector(3 downto 0); -- input to seven segment display
Tap_Output: out STD_LOGIC_VECTOR (8 downto 0);-- Tap output
SSG_out : out STD_LOGIC_VECTOR (6 downto 0);--- SEVEN SEGMENT OUTPUT DISPLAY
AN0 : out STD_LoGIC);
end UPDOWNCOUNTERHOLD;

architecture Behavioral of UPDOWNCOUNTERHOLD is

Constant Max_tap :integer := 9;-- referance for the switches
signal Max_tap_vector:std_logic_vector(3 downto 0);
Signal Auto :STD_LOGIC;---- signal for Automatic
Signal Tap_select :STD_LOGIC;-----signal for Tap_set
Signal Switch :std_logic_vector(3 downto 0);----- signal for SW
Signal Tap_out :std_logic_vector(3 downto 0);----- signal for Tap_Output
Signal Seven_segment :std_logic_vector(6 downto 0);----- signal for the seven segment display
SIGNAL S_SW :std_logic_vector(3 DOWNTO 0);----- SIGANAL FOR SWITCH IN MAUNAL/TAP SELECT
BEGIN
PROCESS(Clock,Reset,Tap_set)

BEGIN

IF (Reset = ''1'') THEN

Tap_out <= "0001"; -- reset to tap 1
Seven_segment <= "1001111" ;-- reset it to display tap 1

ELSIF (rising_edge(Clock)) THEN

IF (Tap_set = ''1'') THEN

Tap_Out<= Switch; -- running on manual output depends on the tap switch which is on

end if;

IF (Tap_out > Max_tap) THEN ---- If the output is more than 9 reset

Tap_Out<= "0001"; --- reset to tap 1
Seven_segment <= "1001111" ;-- reset it to display tap 1

IF (conv_integer(Max_tap)) = Max_tap_vector then

--IF (conv_integer(Max_tap_vector)) = Max_tap then------converting interger
--OTHER_VECTOR<=(others =>''0'');
END IF;
END IF;
End if;
END PROCESS;
PROCESS(SW,Clock)
Begin
--S_SW <= SW(3 DOWNTO 0) ;
case SW is
when "0001"=>SSG_out<= "1001111";
when "0010"=>SSG_out<= "0010010";
when "0011"=>SSG_out<= "0000110";
when "0100"=>SSG_out<= "1001100";
when "0101"=>SSG_out<= "0100100";
when "0110"=>SSG_out<= "0100000";
when "0111"=>SSG_out<= "0001111";
when "1000"=>SSG_out<= "0000000";
when "1001"=>SSG_out<= "0000100";
--nothing is displayed when a number more than 9 is given as input.
when others =>SSG_out<="1111111" ;
end case ;
END PROCESS;
end Behavioral;
?

Related Discussions:- Vhdl

Define hysteresis, Define Hysteresis Hysteresis is the 'lagging' effect...

Define Hysteresis Hysteresis is the 'lagging' effect of flux density B whenever there are changes in the magnetic field strength H. When an initially unmagnetized ferromagnetic

Sequential diagram, 1) Draw the state diagram for the state machine describ...

1) Draw the state diagram for the state machine described by Table 7.5 in the text. Note, the table shows the transition to the next state S* from the current state S for the next

Digital logic circuits, . In successive-approximation A/D converter, offset...

. In successive-approximation A/D converter, offset voltage equal to 1/2LSB is added to theD/A converter’s output. This is done to

Get bode plots of magnitude and phase of transfer function, Develop a PSpic...

Develop a PSpice program and use PROBE to obtain Bode plots of the magnitude and phase of the transfer function ¯V out / ¯V in for the high-pass ?lter circuit shown in Figure (a)

Positive and negative clippers, Positive Clippers The shunt connected p...

Positive Clippers The shunt connected positive clipper, in which the diode conducts for positive half cycle and hence, the output is a straight line. During the negative half c

Finite state machine, the tutorial assignment is part of my thesis work and...

the tutorial assignment is part of my thesis work and i need help in it please

General, a single phase 120 volts, 60hertz supply is connected to a coil of...

a single phase 120 volts, 60hertz supply is connected to a coil of 200 turns wound round a toroidal magnetic core with a mean length 100cm and cross section 20cm square &relative p

Block schematic diagram of ss7, Q. Block schematic diagram of SS7? Leve...

Q. Block schematic diagram of SS7? Levels are as below: Level 1: The Physical Layer Level 2: The Data Link Level Level 3: The signaling network level Level 4: The User Pa

Power diode - power semiconductor devices , Power Diode A power diode i...

Power Diode A power diode is a two terminal, anode a and cathode K and  two layer P  and  N  junction devices. A PN  junction normally  formed  by allowing  diffusion and epita

Describe about absolute poverty, Q. Describe about Absolute Poverty? Po...

Q. Describe about Absolute Poverty? Poverty defined with respect to an absolute material standard of living. A person is absolutely poor if their income does not allow them to

Write Your Message!

Captcha
Order Assignment

Featured Services

Order Now

Popular Subjects

Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

Submit Assignment

Academics

Major Subjects

Majors

Get In Touch

whatsapp: +91-977-207-8620

Phone: +91-977-207-8620

Email: [email protected]

TERMS & POLICIES

HELP & SUPPORT

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd