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Q. Register-to-register operands in RISC?
Register-to-register operands: In RISC machines operation which access memories are LOAD and STORE. All other operands are kept in registers. This design feature make simpler the instruction set and consequently simplifies the CU. For illustrations a RISC instruction set can include only one or two ADD instructions (for example integer add and add with carry); on the other hand a CISC machine can have 25 add instructions including different addressing modes. Another advantage is that RISC encourages optimization of register use so that frequently used operands remain in registers.
Q. Explain about Cathode Ray Tubes? Cathode ray tube is the major technology on that televisions and monitors have been based. CRT is a partially evacuated glass tube which is
Hiding data within the class and making it available only by the methods. This method is used to protect your class against accidental changes to fields, which might leave the clas
Why floating point number more difficult to represent and process than integer? In floating point numbers we have to show any number in three fields sign, exponent and mantissa
INTEL ARCHITECTURE - 64 ( IA-64) IA-64 (Intel Architecture-64) is a 64-bit processor architecture developed in cooperation by Intel and Hewlett-Packard, executed by processors s
What is the use of inter process communication. Inter process communication gives a mechanism to allow the co-operating process to communicate with each other and synchronies t
A device which converts BCD to Seven Segment is called ? Ans. DECODER is a device that converts BCD to Seven Segment. This coverts binary words in alphanumeric characters.
If we have multiple filters impleted, what is the order in which these filters get implemented? Ans) 1. Authorization filters 2. Response filters 3. Action filters
Consider the following linear programming problem: Minimize: 70M + 40N Subject to: 3M + 7N ≥ 233 10M + 2N ≥ 254
Determine the synchronization of bits The synchronization provided by use of start and stop bits, an extra bit known as a parity bit may optionally be transmitted along with th
Dynamic address translation : If, when executing an instruction, a CPU fetches an instruction located at a specific virtual address, or fetches data from a particular virtual
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