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Positive Edge Triggered D Flip Flop
In this type of D flip Flop ( 7475) shown in figure the output changes with positive edge of the CLK when CLK changes from 0 to 1 the output becomes equal to the inputs. There is no change in the output at any other time.
Q. An operational amplifier stage is typically represented by the circuit of Figure. For the values given, determine V out and the power supplied by the 2.5-V source.
how many data input and data output line for 8k 16-bits?
Diffusion Current : The carrier currents are also due to concentration gradients in the doped material which lead to diffusion of carriers from high concentration region to l
Explain time division switching? Time Division Switching: A switching element can be shared by number of concurrently active speech circuits. It is the princi
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Explain the construction and working of Calomel electrode
Q. For a transmission-line model that includes only the series impedance Z, sketch phasor diagrams for: (a) Lagging power factor load. (b) Leading power factor load.
Q. A shift register can be used as a binary (a) divide by-2, and (b) multiply-by-2 counter. Explain. Show a block diagram of a 4-bit shift-right register using JKFFs.
BLOCK DIAGRAM OF DIGITAL CONTROL OF ELECTRIC DRIVES
A 500 MVA, 33kv, three phase steam turbine generator has a synchronous reactance of 1.6 p.u. It delivers a rated output at 0.8 power factor lagging. Calculate (a) The synchronou
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