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The main I/O used by micro controllers are the parallel ports , the 68HC11F1 has seven 8 bit ports namely Port A,B,C,D,E,F and G . The use of ports depends on the mode configuration of the system and the use of the other peripheral devices, since they share pins. In order to program the ports we need to write/read data to special registers, the area from 0x1000 to 0x105f is memory mapped to the peripheral devices. NOTE: The monitor has moved the register block to start at 0x00 i.e Padr = 0x00, Paddr = 0x1 etc.
Below are shown the RAM based I/O registers i.e. 0x0 to 0x0a Address Register 0x0000 Port A register Padr 0x0001 Port A Data direction register Paddr 0x0002 Port G register Pgdr 0x0003 Port G Data direction register Pgddr 0x0004 Port B register Pbdr 0x0005 Port F register Pfdr 0x0006 Port C register Pcdr 0x0007 Port C Data direction register Pcddr 0x0008 Port D register Pddr 0x0009 Port D Data direction register Pdddr 0x000a Port E register Pedr Port A, D, are bi-directional 8 bit ports and have alternate uses G timer, serial comms and chip selects respectively. Port B is an 8 bit general purpose output port with alternate function as the upper address bus in the extended mode. Port C is a general purpose 8 bit port with alternate functions as the data bus in the extended mode Port E is an 8 bit general purpose 8 bit input port with an alternate function as the ADC input Port F is a 8 bit general purpose output port with alternate function as the lower address bus in the extended mode. On the target system provided the 68HC11 is set in extended mode therefore the only ports available are A,D,E and G since B,F form the address bus and C forms the data bus to the EPROM. Each register is bit defined in that each bit configures one feature of the respective port , however all the data registers and data direction registers work on the same principle.
Zero address instruction format is used for (A) RISC architecture. (B) CISC architecture. (C) Von-Neuman architecture. (D) Stack-organized architecture.
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