Modes of 8254-microprocessor, Assembly Language

Assignment Help:

Modes of 8254 :

 

1632_modes of 8254.jpg

Mode 0 (Interrupt on Terminal Count)-GATE which value is 1 enables counting and GATE  which value is 0 disables counting, and GATE put not effect on OUT. The contents of the CR are transferred to CE on the first CLK pulse after CR is written into by the processor, unrelated of the signal on the GATE pin. Pulse that loads CE is not included in the count. OUT would low when there is an output to the control register and remains low till the count goes to 0.Primarily, Mode 0 is for event counting.

Mode 1 (Hardware Re -triggerabic  One-Shot)-After  CR has been loaded  with N, a 0-to-1  transition  on GATE will cause CE to be loaded, a one-to-zero transition  at OUT, and the count to start. When the count reaches to zero OUT will go high so producing a negative-going OUT pulse N clock periods long.

Mode 2 (Periodic Interval Timer)-after loading CR with N, a transfer is occur from CR to CE on the next clock pulse. OUT goes from one  to zero when the count becomes one and remains low for o1 CLK pulse; then it returns to 1 and CE is reloaded from CR, so  giving a negative pulse at OUT after each N clock cycles. GATE that value 1 enables the count and GAT that value is 0 disables the count. A 0-to-1 transition on GATE also causes the count to be reinitialized on the next clock pulse. This mode is utilized to provide a programmable periodic interval timer.

Mode 3 (Square-Wave Generator)-It is likewise to mode 2 except that OUT goes low when half the first count is reached and remains low till the count becomes zero. So the duty cycle is changed. As like before, GATE enables and disables the count and a zero to one transition on GATE reinitializes the count. This mode can be utilized for baud rate generation.

Mode 4 (Software-Triggered  Strobe)-It is likewise to mode 0 except that OUT is high while the counting is taking place and generate a one-clock-period negative pulse when the count reaches zero.

Mode 5 (Hardware-Triggered Strobe-Retriggerabic)-After CR is loaded, a O-to-I transition on GATE will cause a transfer from CR to CE during the next CLK pulse. OUT will be high in the time counting but will go low for one CLK period when the count becomes zero. GATE may reinitialize counting at any time.

For all modes, if the starting count is zero, it will be interpreted as216 or104 depending on the format of the count. The above descriptions were just to provide a whole idea of the operation of the 8254 in the several modes.

 

 


Related Discussions:- Modes of 8254-microprocessor

Introduction to 80 x 86 assembly language, Using the windows32 framework, w...

Using the windows32 framework, write a complete 80x86 program for Programming Exercises 4.3 number 3, on pages 130-131 of the textbook. Follow all coding conventions mentioned in

Memory interface-microprocessor, Memory Interface              ...

Memory Interface                                                                  Figure: Memory Modulation design The memory of a computer contain of number of memo

Cache components-microprocessor, Cache components The cache sub-system ...

Cache components The cache sub-system may be divided into 3 functional blocks: Tag RAM, SRAM and theCache Controller. In real designs, these blocks can be implemented  by multi

Avr, how to code

how to code

Read architecture:look through-microprocessor, Read Architecture: Look Thro...

Read Architecture: Look Through Main memory that located is conflicting the system interface. The least concerning feature of this cache unit is that it remain between the proc

Operating systems, what would be the typical pricing for helping out on Ope...

what would be the typical pricing for helping out on Operating systems 1 assignments at UCI

Code using hla language, You have been hired by the Elbonian government to ...

You have been hired by the Elbonian government to write an Assembly program to help its workforce determine how much their tax will be. The tax laws in Elbonian are very simple. Th

Shr-sar-logical instruction-microprocessor, SHR : Shift Logical Right: Thi...

SHR : Shift Logical Right: This instruction performs bit-wise right shifts on the operand word or byte that might be reside in  a memory location or a register, by the specified c

Comparison between 8086 and 8088, Comparison between 8086 and 8088 All ...

Comparison between 8086 and 8088 All the changes in 8088 above 8086 are indirectly or directly related to the 8-bit, 8085 compatible data and control bus interface. 1) The p

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd