Q. Explain the fixed bias circuit?

          The Fig refers to the common emitter collector characteristics and the ac and dc load lines.The Fig shows the points Q₁ and Q₂ which refers to the operating point at the middle of the dc load line and the point which gives as large as an output possible without too much distortion respectively.

Biasing is usually done to prevent thermal runaway which damages the transistor permanently. One kind of biasing is the fixed bias circuit.

Analyzing the input loop of the circuit by KVL

V_cc=I_bR_b + V_be.

I_b=(V_cc-V_be)/R_b.

I_c=b_Ib.

Analyzing the output loop of the circuit by KVL.

V_cc=I_c+V_ce

V_ce=V_cc-I_c.R_c.

Hence through the input and output loop we have calculated the output current(I_c) and output voltage (V_ce).

The current Ib is constant and the network in the dig 2 is called the fixed bias circuit.

In summary we see that selection point Q depends upon a number of factors. Among these factors are the ac and dc loads of the stage the available power supply the maximum power ratings, the peak signal excursions to be handled by the stage and the tolerable distortion.