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Q. Explain Optimization process of Pipelining ?
RISC machines can use a very efficient pipeline scheme due to the regular and simple instructions. Similarly all other instruction pipelines RISC pipeline suffer from problems of branching instructions anddata dependencies. RISC optimizes this problem by employing a technique known as delayed branching.
One of the common schemes used to avoid branch penalty is to pre-fetch branch destination also. RISC follows a branch optimization scheme known as delayed jump as displayed in the illustration given below:
(a) The instruction "If RD< 0 Return" may cause pipeline to empty
(b) The No operation instruction causes decision of the If instruction known, thus correct instruction can be fetched.
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can i get the comparison of microprocessors architecture?
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