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Digital system, Electrical Engineering

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1- Use 4-to-16 decoder and some residue gates to recognize the following functions
F1(A,B,C)= S(1,2,4,5,7)
F2(A,B,C,D)= S(1,2,4,5,7,10,12,14,15)
F3(A,B,C,D,E)= S(1,2,4,5,7,10,12,14,15,19,23,25,27,29,31)



2- Use n 8-to-1 MUX to realize the following function:
F(A,B,C,D,E)= BDE’ + A’BD’ + A’C’D’ + C’DE’




3- Design 3x8 ROM where the following bit patterns are burned into the following consecutive memory locations starting from 0.
10101010
00110011
11110011
11001100
00011100
11100011
01111011
00111110




4- To realize the following functions specify the minimum size of a PAL in terms of required inputs, outputs, and OR gates. Also draw the figure for PAL implementation of these function using minimum size PAL.
F1(A,B,C,D,E)=ACD’ + B’C’E’ +ADE+A’BCD
F2(A,B,C,D)=AC+AC’D+BCD’+A’B’D
F3(A,B,C,D,E)=A’B’C+B’C’+ACD’+BC



5- Design a circuit that accepts two 4-bit numbers A and B. If both numbers are less than 10, then A will be added to as two BCD digits, if at least one the numbers is greater than 9 then A will be added to B as two decimal numbers. The addition must use fast adders. A flag should be turned on to indicate the sum and the carry is in BCD. When flag is off it means that the result is in decimal. You may assume you have 1-bit adders. The LAC will be your responsibility. For comparators, decoders, and multiplexers you may assume you have them in any size as you need size as you need them, Also residue gates are available as you need them.

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