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N number of XNOR gates is linked in series that is the N inputs (A0, A1, A2......) are specified in the subsequently way: A0 and A1 to first XNOR gate and A2 and O/P of First XNOR to second XNOR gate and many more..... Nth XNOR gates output is last output. How does this circuit work? Describe in detail?
When N=Odd, the circuit works as even parity detector, which is the output will 1 when there are even number of 1's in the N input...that could also be termed as odd parity generator as with this additional 1 as output the total number of 1's will be ODD. When N=Even, just the opposite, that will be Odd parity detector or Even Parity Generator.
The device is packaged in a 80 pin PLCC device as shown.The main groupings of the pins are as follows Port A PA0 - PA7 Parallel Port or Timer Port B PB0 - PB7 Parallel Port or High
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