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Design a counter modulo 4 (sequential circuit with two flip-flops and one input U) which work like that:
1. When U=0, the state of the flip-flop does not change.
2. When U=1, the state sequence is code Gray 11, 10, 00, 01 and repeat.
a. implement with D flip-flops
b. implement with J K flip-flops
c. implement with T flip-flops
Specify how initialize the initial state of the counter
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If the input to T-flipflop is 100 Hz signal, the final output of the three T-flipflops in cascade is ? Ans. The final output of the three T-flip-flops in cascade is 12
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