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Q. Design a half adder?
In half adder inputs are:
The augend let's say 'x' and addend 'y' bits.
The outputs are sum 'S' and carry 'C' bits.
Logical relationship between these are given by truth table as displayed in figure (a). Carry 'C' can be attained on implementing AND gate on 'x' & 'y' inputs so C = x.y whereas S can be found from Karnaugh Map as displayed in figure (b). Corresponding logic diagram is displayed in figure (c).
So sum and carry equations of half- adder are:
S = x.y¯ + x¯.y
C = x.y
Figure: Half - Adder implementation
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