Design a bcd to seven segment decoder, Computer Engineering

Assignment Help:

Design a BCD to seven segment decoder that accepts a decimal digit in BCS and generates the appropriate output for segments in display indicator.

Ans:

BCD-TO-seven-Segment Decoder: A digital display which consists of seven LED segments is commonly utilized to display decimal numerals in digital systems. Various familiar illustrations are electronic calculators and watches where one 7-segment display device is utilized for displaying one numeral 0 through 9. To use this display device, the data has to be converted by some binary code to the code essential for the display. Frequently the binary code utilized is Natural BCD. Fig.(a) demonstrates the display device. Fig.(b) demonstrates the segments that should be illuminated for each of the numerals and Fig.(c) provides the display system.

144_BCD to seven segment decoder.png

                                  Fig.(a)                                                   Fig.(b)

1346_Design a BCD to seven segment decoder.png

Fig.(c)

Table 1 provides the truth table of BCD-to-7-segment Decoder. Now there ABCD is the Natural BCD code for numerals 0 throughout 9. The K-maps for all of the outputs a through g are specified in Fig.(d), (f),(h),(j),(l),(n),(p). The whole in the K-map corresponding to 6 binary combinations not utilized in the truth table are X -don't care.

Decimal      Digit

Displayed

 

Inputs

 

 

 

 

 

Outputs

 

 

 

 

A

B

C

D

a

b

c

d

e

f

g

0

0

0

0

0

1

1

1

1

1

1

0

1

0

0

0

1

0

1

1

0

0

0

0

2

0

0

1

0

1

1

0

1

1

0

1

3

0

0

1

1

1

1

1

1

0

0

1

4

0

1

0

0

0

1

1

0

0

1

1

5

0

1

0

1

1

0

1

1

0

1

1

6

0

1

1

0

0

0

1

1

1

1

1

7

0

1

1

1

1

1

1

0

0

0

0

8

1

0

0

0

1

1

1

1

1

1

1

9

1

0

0

1

1

1

1

0

0

1

1

Tableno.1 Truth Table of BCD-to-7 Segment Decoder

(i) K-map and Logic Diagram for Digital Output 'a':

1603_Logic Diagram for Output a.png

For the Fig.(d) the simplified expressions is given by a =  B‾ D‾  + BD + CD + A and the logic diagram is demonstrated in Fig.(e)

648_Logic Diagram for Output e.png

Fig.(e) Logic Diagram for Output 'a'

(ii) K-map and Logic Diagram for Digital Output 'b':

1015_Logic Diagram for Output f.png

For the Fig.(f) the simplified expressions is specified by b =  B‾ +  C‾D‾  + CD and the logic diagram is demonstrated in Fig.(g)

1964_Logic Diagram for Output b.png

Fig.(g) Logic Diagram for Output 'b'

(iii) K-map and Logic Diagram for Digital Output 'c':

 

761_K-map and Logic Diagram for Digital Output.png

For the Fig.(h) the simplified expressions is specified by c = B + C‾ + D and the logic diagram is demonstrated in Fig.(i)

2216_logic diagram is demonstrated in i.png

Fig.(i) Logic Diagram for Output ' c '

(iv) K-map and Logic Diagram for Digital Output'd':

747_K-map and Logic Diagram for Digital Output d.png

The simplified expressions for the Fig.(j) is given by

d = B‾D‾ + CD‾ + B‾C +BC‾D and the logic diagram is demonstrated in Fig.(k)

70_Logic Diagram for Output d.png

Fig.(k) Logic Diagram for Output ' d '

(v) K-map and Logic Diagram for Digital Output 'e':

1180_K-map and Logic Diagram for Digital Output e.png

For the Fig.(l) the simplified expressions is specified by e =  B‾D‾  + CD‾  and the logic diagram is demonstrated in Fig.(m)

1466_Logic Diagram for Output m.png

Fig.(m) Logic Diagram for Output 'e'

 (vi) K-map and Logic Diagram for Digital Output 'f':

451_K-map and Logic Diagram for Digital Output f.png

For the Fig.(n) the simplified expressions is specified by f = A + C‾ D‾  + BC‾  +BD‾  and the logic diagram is demonstrated in Fig.(o)

1170_Logic Diagram for Output n.png

Fig.(o) Logic Diagram for Output ' f'

(vii) K-map and Logic Diagram for Digital Output 'g':

 

936_K-map and Logic Diagram for Digital Output b.png

For the Fig.(p) the simplified expressions is specified by g = A + BC‾ + B‾C+ CD‾  and the logic diagram is demonstrated in fig.(q).

743_Logic Diagram for Output 1.png

Fig.(q) Logic Diagram for Output ' g '


Related Discussions:- Design a bcd to seven segment decoder

What is single program multiple data, Q. What is Single Program Multiple Da...

Q. What is Single Program Multiple Data (SPMD) SPMD is in fact a "high level" programming model which can be built on any arrangement of previously described parallel programmi

Vector reduction instructions-vector processing, Vector reduction Instructi...

Vector reduction Instructions : When operations on vector are being deduced to scalar items as the result, then these are the vector reduction instructions. These instructions are

Block diagram of an associative memory, Q. Block diagram of an associative ...

Q. Block diagram of an associative memory? The block diagram of an associative memory is displayed in Figure below. It comprises of a memory array and logic for m words with n

Explain shared memory system and tightly coupled system, Shared Memory Syst...

Shared Memory System / Tightly Coupled System Shared memory multiprocessors have the subsequent features: For real-time high-speed processing these systems are preferabl

Find out data changing from special code to temporal code, Data can be chan...

Data can be changed from special code to temporal code by using ? Ans. By using Shift Registers data can be changed from special code to temporal code. A Register wherein data ge

Write an assembly function which hides the cursor, Q. Write an assembly fun...

Q. Write an assembly function which hides the cursor? Write an assembly function which hides the cursor. Call it from a C program.             . PUBLIC CUROFF

Basic performance equation, Explain the basic performance equation Ans...

Explain the basic performance equation Ans: The basic performance equation is following T = N * S/ R T =>  It is processor time required to execute a program N => act

Inventor, I am the inventor of the railway signaling device now operated by...

I am the inventor of the railway signaling device now operated by timer. I wish to move on to the next phase where the equipment will be operated by DTMF codes. The device is a si

What is organizational structure, What is Organizational Structure? A b...

What is Organizational Structure? A business organization may be structured in many dissimilar ways, depending upon the environment within which it handles.  There is always

Perform multiplication with showing content of accumulator, Perform multipl...

Perform multiplication with showing the contents of accumulator, B register and Y register during each step. (Accumulator, B, Y are 4-bit registers) B=06 Y=02

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd