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Digital Systems
1. Describe the working of Binary comparator (Magnitude comparator)a. Define Binary comparatorb. Binary comparator working process with logical diagrams
2. Describe the working of Parity generators and checkers.a. Define Parity generators and checkersb. Parity representation for Binary number table and explanationc. Detecting an Error using Parity generators and checkers with example
3. Describe the working principle of Master-slave J-K flip-flop.a. Define J-K flip-flopb. Working principle of Master-slave J-K flip-flopc. Logic diagram and truth table
4. Explain the working of negative edge triggered ripple up-counter.
5. With the block diagram justify the working of Flash ADC.
One of the simplest circuits is the asynchronous or ' ripple' counter. Below is shown the circuit diagram of a simple 3 stage ripple counter. The operation of this circuit
Solid-State Control of Synchronous Motors The speed of a synchronous motor can be controlled by changing its supply frequency. With variable-frequency control, two modes of op
describe the working and construction diagram of nicholas prism
How control and monitoring has be done - Sensors gather information from application being monitored or controlled. - The data being gathered is frequently analogue in natur
Q. A shunt generator gives full load output of 30 kW at a terminal voltage of 200V. The armature and field resistance are 0.05? and 50? resp.. The iron and friction losses are 10
how to measure
Calculate the following for a 2 hp and a 20 hp dc machine, each rated for 500 rpm. Use data from the Study Plan 1 data sheet, including "hot" armature resistance value for all cal
Q. Designing 100 line exchange using Uni-selector? Here three different designing methods for 100 line exchange are discussed: Design: Strowger switching system is designe
Q. For a 6-bit weighted-resistor D/A converter, if R is the resistor connected to the MSB, find the other resistor values needed, and calculate the maximum analog output voltage, t
What is meant by polling? In polling schemes, a set of address lines is driven by the controller to address every of the masters in sequence. When a bus request is received fro
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