Obtain expressions for the drain source current in an n-channel MOS transistor in terms of terminal voltages and transistor parameters. Indicate reasons why, for deep sub micron transistors found on ASICs, simple theory may overestimate the drain-source current in saturation by a factor of 2 or more.

Combinational logic cells in CMOS are often formed from efficient AND-OR-INVERT (AOI) and OR-AND-INVERT (OAI) complex cells using series - parallel networks of transistors (stacks). Describe the design procedure used illustrating the process by designing an OAI 321 cell at transistor level. Equal drive strengths are required.