D Flip Flop

As we have seen  in the SR flip flop  when the inputs  S= R  are applied the forbidden or indeterminate state occurs.  This state can destabilize the SR file flop. It can be avoided by D flip flop. The  D flip flop can be constructed using SR flip flop. The  D flip flop  has one  inputs  D and a clock  inputs.  The logic diagram of D flip  flop  is shown in figure.

The  D input is directly  connected to the S input  and its  complement is connected to R input. since  the output  is delayed because the output  does  not change  immediately when the clock  pulse goes  from 0 to 1  the inputs  is thus delayed by a clock  pulse  before  appearing  at the output. So  it is also  known  as delay flip  flop.