Reference no: EM131662640
1. You have a PC with a 2 GHz processor, a system bus clocked at 400 MHz, and a 3 Mbps internal cable modern attached to the system bus. No parity or other error-checking mechanisms are used. The modern has a 64-byte buffer.
After it receives 64 64 bytes, it stops accepting data from the network and sends a data ready interrupt to the CPU. When this interrupt is received, the CPU and OS perform the following actions:
1. The supervisor is called.
2. The supervisor calls the modern's data ready interrupt handler.
3. The interrupt handler sends a command to modern, instructing it to copy its buffer content to main memory.
4. The modern interrupt handler immediately returns control to the supervisor' without waiting for the copy operation to be completed.
5. The supervisor returns control to the process that was originally interrupted.
When the modern finishes the data transfer, it sends a transfer completed interrupt to the CPU and resumes accepting data from the network. In response to the interrupt, the CPU and OS perform the following actions:
1. The supervisor is called.
2. The supervisor calls the transfer completed interrupt handler.
3. The interrupt handler determines whether a complete packet is present in memory. If so, it copies the packet to a memory region of the corresponding application program.
4. The modern interrupt handler returns control to the supervisor.
5. The supervisor returns control to the process that was originally interrupted.
6. Consider the following binary value :
1000 0000 0010 0110 0000 0110 1101 1001
what number (base 10 ) is represented if the value is assumed to represent a number stored in twos complement notation ? Excess notation? IEEE binary32 floating-point notation?
7. You have a CPU with a 4.8 GHz clock rate. Both the instruction and execution cycles are 50% of the clock cycle. The average instruction requires 0.5 nanoseconds to complete execution. Main memory access speed for a single instruction is 2 nanoseconds on average. What is the expected average MIPS rate for this CPU ? What modern microprocessor architectural features might be added to the CPU to improve its MIPS rate?
8. What factors limit the speed of an electrically based processing device ?
9. What is a font? What is pont size?
10. Describe the types of optical input devices. For what type of input is each device intended ?