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Q1) Consider a 5-stage pipeline where the branch address is resolved in the second stage and the branch condition is resolved in the third stage. Assume that 20% of the instructions in a typical instruction mix are branch instructions, and that the probability that the branch is taken is 60%.
a. What is the effect of control hazards on the CPI for this pipeline? Consider the two cases of "predict branch not taken" and "predict branch taken".
b. Assume that it is possible to move the resolution of the branch condition from the third to the second stage, but that this will require a 4% increase in the cycle time. Would this change result in a more efficient pipeline? (Again consider both the branch taken and not taken predictions).
c. If the architecture uses a delayed-branch instruction, and the compiler can fill up the delay slot by a useful instruction 30% of the time, how much would that improve the CPI for each of the above architectures. Here only consider the case of "predict branch not taken.
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