Simulate the system to demonstrate correct behavior

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Reference no: EM131096968

SECTION 9.4: DATAPATH COMPONENT DESCRIPTION USING HARDWARE DESCRIPTION LANGUAGES

(a) Create a behavioral HDL description of an 8-bit parallel load register with load and clear control inputs (both synchronous: clear has priority over load).

(b) Create a testbench to test the description, testing load, clear, simultaneous load/clear, and holding the register value.

Reference no: EM131096968

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