Register and combinational logic

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Use the RTL design process to create a 4-bit up-counter with input cnt (1 means countup), clear input clr, a terminal count output tc, and a 4-bit output Q indicating the presentcount. Terminal count output tc should be 1 only when the 4-bit counter output is 1111. Thecounter rolls over to 0000 after 1111 (if cnt is asserted for counting up). After deriving thecontroller's FSM, implement the controller as a state register and combinational logic.

Reference no: EM131069654

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