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Design and simulate a common-drain amplifier

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Reference no: EM132240191

Analog IC Design - Mentor Tools Lab - Common Drain Frequency Response

Learning Objectives - In this lab you will:

  • Design and simulate a common-drain amplifier.
  • Learn how to generate and use design charts.
  • Learn how to do ac, DC, and transient simulations of a CD amplifier.
  • Investigate the ringing and peaking problem in a capacitive-loaded CD amplifier with a large signal source resistance (Rsig) and learn how to solve it.
  • Use PMOS input transistor to avoid body effect in a CD amplifier.

Part 1: Sizing Chart

In Part 1 you learned:

  • How to generate and use design charts for NMOS and PMOS transistors.
  • How to design a PMOS common-drain amplifier.
  • How the overdrive voltage of a MOS transistor deviates from the square law in different regions of operation.

Note - Detailed Question of Part 1 is in attached file.

PART 2: CD Amplifier

1. OP (Operating Point) Analysis

1) Create a new schematic for the CD amplifier (the schematic is not included in the lab document and is left for the student as an exercise). Use a PMOS and use a 10μA ideal current source for biasing (note that the current source will be connected to the source terminal). Connect the source to the bulk. Use L = 1μm and W as determined in Part 1. Use CL = 2pF, Rsig =2MΩ, and a DC input voltage = 0V.

2) Simulate the OP point. Report a snapshot clearly showing the following parameters (add a filter to your monitor).

ID

VGS

VDS

VTH

VDSAT

GM

GDS

GMB

CDB

CGD

CGS

CSB

Region

3) Check that the transistor operates in saturation.

2. AC Analysis

1) Perform AC analysis (1Hz: 10GHz, logarithmic, 20points/decade) to investigate the frequency domain peaking.

2) Report the Bode plot magnitude.

3) Do you notice frequency domain peaking? Use the following expression to calculate the peaking in dB (or use Measures):

.EXTRACT AC LABEL= Peak(Max(VDB(OUT)))

4) Analytically calculate quality factor (use approximate expressions). Is the system underdamped or overdamped?

5) Perform parametric sweep: CL = 2p, 4p, 8p.

  • Report Bode plot magnitude overlaid on same plot.
  • Report the peaking vs CL. Use this command (if you use already use the .EXTRACT command): .PLOT EXTRACT(Peak)
  • Comment.

6) Perform parametric sweep: Rsig = 20k, 200k, 2M.

  • Report Bode plot magnitude overlaid on same plot.
  • Report the peaking vs Rsig.
  • Comment.

3. Transient Analysis

1) Use a pulse source (pulse_v_source) as your transient stimulus and set it as follows (delay = 2us, initial = 0V, period = 8us, pulse_value = 100mV, t_fall = 1ns, t_rise = 1ns, width = 4us). Run transient analysis (max step = 10n) for 10us to investigate the time domain ringing.

2) Report Vin and Vout overlaid vs time

3) Calculate the DC voltage difference (DC shift) between Vin and Vout.

  • What is the relation between the DC shift and VGS?
  • How to shift the signal down instead of shifting it up?

4) Do you notice time domain ringing? Use the following command to calculate the maximum overshoot as a percentage (replace Vfinal and Vstep with the actual numbers from simulation): .EXTRACT TRAN LABEL=overshoot abs((MAX(V(OUT)) -Vfinal)/Vstep)*100

5) Perform parametric sweep: CL = 2p, 4p, 8p.

  • Report Vout vs time overlaid on same plot.
  • Report the overshoot vs CL. Use this command (keep the previous command as well): .PLOT EXTRACT(overshoot)
  • Comment.

6) Perform parametric sweep: Rsig = 20k, 200k, 2M.

  • Report Vout vs time overlaid on same plot.
  • Report the overshoot vs Rsig.
  • Comment.

4. Zout (Inductive Rise)

1) We want to simulate the CD amplifier output impedance. Replace CL with an AC current source with magnitude = 1. Remove the AC input signal.

2) Perform AC analysis (1Hz:10GHz, logarithmic, 10points/decade). The voltage across the AC current source is itself the output impedance.

3) Plot the output impedance (magnitude and phase) vs frequency. Do you notice an inductive rise? Why?

4) Does Zout fall at high frequency? Why?

5) Analytically calculate the zeros, poles, and magnitude at low/high frequency for Zout. Compare with simulation results in a table.

5. How to solve the peaking/ringing problem?

1) Place the input/output poles away from each other (as we did when we swept CL and Rsig).

2) (This part is optional) A compensation network can be used to compensate for the negative input impedance and prevent overshoots. Read [Johns and Martin, 2012] Section 4.4 and try to implement the compensation network.

In Part 2 you learned:

  • How to do ac, DC and transient simulations of a CD amplifier.
  • How the peaking in the frequency response of a CD amplifier changes with the load capacitor and source resistance.
  • How the ringing in the transient response of a CD amplifier changes with the load capacitor and source resistance.
  • How the output impedance of a CD amplifier shows inductive behavior.

Attachment:- Assignment File.rar

Reference no: EM132240191

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