Design a finite state machine to enable use of write buffer

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Reference no: EM131318750

1. What should happen if the processor issues a request that hits in the cache while a block is being written back to main memory from the write buffer?

2. What should happen if the processor issues a request that misses in the cache while a block is being written back to main memory from the write buffer?

3. Design a finite state machine to enable the use of a write buffer.

Reference no: EM131318750

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