Reference no: EM131439802

Lab Assignment

Objectives:

Gain more experience with modular circuit design
Gain experience with arithmetic circuits including: Full Adders, Ripple Carry Adders (RCAs), and Two's Complement

Lab Description:

You will design a ripple-carry adder (RCA) using full adders as components. You will then use this RCA to implement a two's complement conversion circuit and adapt it to add two numbers with two's complement. You will again use modular or structural design techniques to create these larger digital systems.

Lab Tasks:

1. Design a Ripple Carry Adder to add two 4-bit numbers:

a. Create a VHDL design module for a Full Adder; use Boolean expressions to define this circuit. Create a VHDL test bench to test the output for all possible input signal combinations. Simulate your design and verify your output.

b. Create a VHDL design module for this 4-bit Ripple Carry Adder (RCA):

i. You will have two 4-bit inputs (you can call them A and B), one 1-bit carry-in input, one 4-bit sum output, and one 1-bit carry-out output. Use the Full Adder VHDL module you just created. Specifically, use a component declaration and port mapping to create a modular design that uses your pre-existing work.

ii. How will you design this circuit? How many Full Adders and other gates will you need in order to create this 4-bit RCA? Draw a block diagram/schematic of your design including any components or logic gates. Label the components that you do use (e.g. Full Adders). You will include this block diagram/schematic in your report.

c. Create a VHDL test bench to test the output for all possible input signal combinations, wait a minute, how many input combinations will this be?!? Instead, simulate your design using five pairs of input numbers and verify your output. Include the waveforms in your report.

d. Further test your circuit by implementing this on the FPGA board. Connect the input busses of A and B to eight switches, set carry-in to one button, and connect the output bus and carry-out to five LEDs.

2. Design a circuit to take the Two's Complement of a 4-bit number:

a. In the same project, create a new VHDL design module and add the components that you will need to implement the 4-bit Two's Complement circuit:

i. You will have one 4-bit input and one 4-bit output. You will again use component declaration and port mapping to create a modular design.

ii. How will you design this circuit? How many Full Adders and other gates will you need in order to create this 4-bit Two's Complement circuit? Draw a block diagram/schematic of your design including any components or logic gates. Label the components that you do use (e.g. RCA, Full Adders, etc.). You will include this block diagram/schematic in your report.

b. Create a VHDL test bench to test the output for all possible input signal combinations. Simulate your design and verify your output. Include the waveforms in your report.

3. Lastly, design a circuit to add two 4-bit numbers where one number can be expressed in Two's Complement:

a. In the same project, create a VHDL design module for a 4-bit RCA using Two's Complement:

i. This will be a modular design which will use VHDL component declarations and port mapping. This time, you will have two 4-bit inputs (you can call them A and B), one 1- bit select input, and one 4-bit sum output. If the select bit is 1, then the Two's Complement of input number B will be added to A. If the select bit is 0, then the sum is just A + B.

ii. How will you design this circuit? There is a more efficient way than to use your 4-bit RCA from Lab Task 1 and your Two's Complement circuit from Lab Task 2. If you are stumped, think about using every Full Adder input of a RCA, and think about how you will now use the select input.

iii. Draw a block diagram/schematic of your design including any components or logic gates. Label the components that you do use (e.g. Full Adders, RCA, Two's Complement circuit, etc.) and within each component, show the Full Adders and logic gates that are within the component. You will include this block diagram/schematic in your report.

b. Create a VHDL test bench to test the output for five pairs of input numbers (and don't forget to try toggling the select input). Simulate your design and verify your output.

c. Implement this circuit on the FPGA board. Connect the input busses to eight switches, connect the select input to a button, and connect the output bus to four LEDs.

d. Ask the instructor to check your design, simulation waveforms, and FPGA board implementation of your circuit

4. Once you have completed the lab tasks, and after you close this project, remember to copy your project folder to a flash drive, your Dropbox, your Google Drive, or your email in order to keep a copy of your files.

VHDL Code:

Copy-paste your VHDL design module code for:

1. Your full adder and ripple-carry adder (task 1):

2. Your two's complement circuit (task 2):

3. Your ripple-carry adder using two's complement (task 3):

Simulation Screenshots:

Use the "Print Screen" button to capture your screenshot (it should show the entire screen, not just the window of the program).

1. Your ripple-carry adder (task 1):

2. Your two's complement circuit (task 2):

Simulation Screenshot Tips: (you can delete this once you capture your screenshot)

1. Make the "Wave" window large by clicking the "+" button near the upper-right of the window

2. Click the "Zoom Full" button (looks like a blue/green-filled magnifying glass) to enlarge your waveforms

3. In order to not print a lot of black, change the color scheme of the "Wave" window:

3.1. Click Tools→Edit Preferences...

3.2. The "By Window" tab should be selected, then click Wave Windows in the "Window List" to the left

3.3. Scroll to the bottom of the "Wave Windows Color Scheme" list and click waveBackground. Then click white in the color "Palette" at the right of the screen.

3.4. Now color the waveforms and text black:

3.4.1. Click LOGIC_0 in the "Wave Windows Color Scheme." Then click black in the color "Palette" at the right of the screen.

3.4.2. Repeat this for LOGIC_1, timeColor, and cursorColor (if you have a cursor you want to print)

3.5. Once you have captured your screenshot, you can click the Reset Defaults button to restore the "Wave" window to its original color scheme.

Questions: (Please use this cover sheet to type and print your responses)

1. Explain the design process that you used to create the RCA and Two's Complement circuits (lab tasks 1 and 2). Be sure to refer to your schematics/block diagrams and the process to translate these into VHDL.

2. When adding two 4-bit numbers together, an addition overflow may occur and carry-out will be ‘1'. Why is this a problem if we are adding unsigned numbers? Why may this be beneficial if we are adding signed numbers (using two's complement)?

3. Explain the design process that you used to create the 4-bit RCA using Two's Complement (lab task 3). Be sure to refer to your schematics/block diagrams and the process to translate these into VHDL.

As a follow-up question, do you feel that your design is optimal (please explain)? Is there any way you could have better minimized your use of full adders and logic gates (please explain)?

4. Give two reasons why we may not want to create a test bench to simulate a circuit using all possible input signal combinations: