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Part a) Consider architecture A that has the addressing modes below for the ADD instruction. Based on the ADD instruction, is this architecture better be encoded as a fixed-length instruction or a variablelength instruction. Give numerical examples to support your answer.
ADD <reg>, <reg> ADD <reg>, <16-bit constant> ADD <reg>, <memory address: reg1+reg2+32-bit displacement>
Part b) The architecture B below supports only these modes for the ADD instruction. Based on the ADD instruction, is this architecture better be encoded as with fixed-length instructions or variable-length instructions. Give numerical examples to support your answer.
ADD <reg>, <reg>, <reg> ADD <reg>, <reg>, <12-bit constant>
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