Computing cycles to save if registers are available

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Q1) Some authors have advocated that target address computations for branch and register comparison be both done in ID stage, arguing that comparison can be done very fast (e.g., at same time as source registers are copied in the ID/EX register).

(a) What changes are to be made to forwarding unit and the stalling control unit in order to implement this optimization?

(b) How many cycles will be saved if both registers are available?

Reference no: EM1345450

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