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Q. What is the significance of giving a negative voltage to the gate higher than that of the source?
This is done to reach the saturation at a lower of level of VDS. The resulting saturation level for ID has been reduced and the fact will continue to decrease as VGS is made more and more negative. Eventually, VGS when VGS = - VP will be sufficiently low to establish a saturation level that is essentially 0mA (practically it is turned off).
Followings are some disadvantage a. Higher latching and holding current b.Higher on state voltage drop and power losses c.Higher gate current d.Higher gat
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