Sr flip flop - introduction to microprocessors , Electrical Engineering

SR Flip Flop

The SR  flip  flop is an arrangement  of logic gates that maintain astable output even after  the  input  are turned off.  It has  two  inputs namely  SET input (S)  and RESET input ( R) and two outputs Q and Q. In a SR flip flop activating the SET input  will switch  it to the other state. Classical SR flip  flop  requires two NAND gates or two NOR  gates. The block  diagram of SR  flip flop is shown in the outputs  of a basic  SR  flip  flop  SR  flip flop  change  whenever  its R or S change  appropriately. The SR flip  flop  can be implemented by using  NOR or NAND  gates  as follows.

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