Split Bus Operation - universal serial bus :
USB 2.0 devices utilize a special protocol in the reset time that is called "chirping", to negotiate the high speed mode having the host/hub. A component that is HS capable first connects as an FS components (D+ pulled high), but upon retaining a USB RESET (both D+ and D- driven LOW by host for 10 to 20 mS) it pulls the D- line high which is known as chirp K. it indicates to the host that the device is high speed. If the host/hub is also HS capable then it chirps (returns alternating K and J states on D+ and D- lines) letting the components know that the hub will operate at high speed. The device has to retain at least 3 sets of KJ chirps before it changes to high speed terminations and start high speed signaling. Because USB 3.0 use wiring separately and in additional to that used by USB 2.0 and USB 1.x that type of speed negotiation is not needed. Clock tolerance power is 480.00 Mbit/s ±500 ppm, 12.000 Mbit/s ±2500 ppm, 1.50 Mbit/s ±15000 ppm.
While high speed components are commonly referred to as "USB 2.0" and advertised as "up to 480 Mbit/s", not all USB 2.0 are high speed components. The USB-IF certifies devices and provides licenses to use special marketing logos for either high speed or basic speed (low and full) after passing a compliance test and paying a licensing fee. All of the devices are tested according to the latest specification, so newly-compliant low speed devices are also 2.0 devices.