History of parallel computers, Computer Engineering

Assignment Help:

History Of Parallel Computers

The test with and implementations of the utilize of parallelism started year back in the 1950s by the IBM.  The IBM enlarges computers also called as IBM 7030 was building in 1959.  In the design of these computers, a number of new ideas like overlapping I/O with processing and instruction look ahead were established.  A serious advance towards designing similar computers was going ahead with the development of ILLIAC IV in 1964 at the University of Illinois.  It had an only control unit but have multiple processing elements. On this machine, at a time, a one operation is executed on dissimilar data items by diverse processing elements. The idea of pipelining was begin in computer CDC 7600 in 1969.  It takes pipelined arithmetic unit.  In the years 1970 to 1985, the study in this area was decided on the development of vector super computer.  In 1976, the CRAY1 was determined by Seymour Cray.  Cray1 was a pioneering effort in the enlargement of vector registers. It accessed main memory only for store and load operations. Cray1 never use optimized pipelined arithmetic unit and virtual memory.  Cray1 had timer speed of 12.5 n.sec. The Cray1 processor evolved upto a speed of 12.5 Mflops on 100 × 100 linear equation solutions. The next invention of Cray called Cray XMP was introduced in the years 1982-84.  It was attached with 8-vector supercomputers and it is used a shared memory also.

Apart from Cray, the giant company developing, Control Data Corporation (CDC), parallel computers of USA, formed supercomputers, the CDC 7600. Its vector supercomputers named Cyber 205 had memory to memory architecture that is, input Vector operands were flow from the main memory to the vector arithmetic unit and the outputs were accumulated back in the main memory.  The benefit of this architecture was that It did not maximize the size of vector operands. The drawback was that it essential required a very high speed memory so that there would be no speed mismatch between main memory and vector arithmetic units.  Developing such high speed memory is very expensive. The Clock hustle of Cyber 205 was 20 n.sec. In the 1980s Japan also going ahead for manufacturing high performance vector supercomputers. Companies like, Fujitsu, Hitachi and NEC were the core manufacturers.  Hitach Established S-810/210 and S-810/10 vector supercomputers in 1982. All these equipment used semiconductor technologies to accomplish speeds at par with Cyber and Cray.  But their vectorisers and operating system were inferior than those of American companies.


Related Discussions:- History of parallel computers

Define the heat transfer processes, Heat Transfer Coursework An interna...

Heat Transfer Coursework An internal combustion engine of a passenger car is operating at steady state conditions e.g. constant speed (r.p.m.) and load (torque), so the engine

client will now send ten integers , Change this program so that every clie...

Change this program so that every client will now send ten integers and receives their sum from the server. In Java, for loops can be easily executed as follows: for (int i = 0 ; i

Platform assignment system, Platform assignment system for the trains in a ...

Platform assignment system for the trains in a railway station cpp program

Discuss the classifications of switching systems, Discuss the classificatio...

Discuss the classifications of switching systems. The categorizations of switching systems are specified in the block diagram given below:

Define compilers and interpreters with high level language, Define compiler...

Define compilers and interpreters with high level language? Both compilers and interpreters are available for most high-level languages. Though LISP and BASIC are in particular

Explain arithmetic shift micro-operations, Q. Explain arithmetic shift Micr...

Q. Explain arithmetic shift Micro-operations? In arithmetic shift a signed binary number is shifted to right or to the left. So an arithmetic shift-left causes a number to be m

Explain the fetch cycle, Q. Explain the Fetch Cycle? The beginning of e...

Q. Explain the Fetch Cycle? The beginning of every instruction cycle is the fetch cycle and causes an instruction tobe fetched from memory.   The fetch cycle comprises four

Define windows authentication, Windows Authentication This provider uti...

Windows Authentication This provider utilizes the authentication capabilities of IIS. After IIS completes its authentication, ASP.NET uses the authenticated identity's token to

How is EISA bus different from ISA bus, How is EISA bus different from ISA ...

How is EISA bus different from ISA bus? Extended Industry Standard Architecture (EISA) is a 32 bit modification to ISA bus. As computers became larger and had wider data buses,

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd