Sources of power dissipation in cmos logic, Electrical Engineering

Describe the three main sources of power dissipation in CMOS logic. Hence calculate the power dissipated in a CMOS ASIC of 40,000 gates operating at a frequency of 133MHz with a supply voltage of 3.3V.

Assume each gate has an output capacitance of 0.15pF and that, on average, 25% of the gates toggle per clock cycle. The ASIC is packaged in a 68 pin CPGA package (assume one buffer/pin) with each buffer taking 8mA, a gain factor bF of 0.01AV-1 and rise/fall times of 2ns. Assume the threshold voltages of the transistors are 0.65V and that each buffer has an output load of 10pF. Assume leakage currents are zero.

Posted Date: 3/16/2013 2:08:22 AM | Location : United States







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