Pci bus transactions - computer architecture, Computer Engineering

PCI bus transactions:

PCI bus traffic is prepared of a series of PCI bus transactions. Each transaction is build up of an address phase that is followed by 1 or more data phases. Direction of the data phases can be from initiator to target (write transaction) or vice-versa (read transaction), but all of the data phases ought to be in the similar direction. Either party can pause or halt the data phases at any specific point. (One common instance is a low-performance PCI device that does not support burst transactions, and always halts a transaction after the first data phase.)Any PCI device can initiate a transaction. Firstly, it might request permission from a PCI bus arbiter on the motherboard. The arbiter gives permission to 1 of the requesting devices. The initiator start the address phase by broadcasting a 32-bit address plus a 4-bit command code, then waits for an objective to respond. All other devices inspect this address and one of them responds a few cycles later.

64-bit addressing is done by using a 2-stage address phase. The initiator broadcasts the low 32 bits address, accompanied by a special "dual address cycle" command code. Components that don't support 64-bit addressing may not respond simply to that command code. In the next cycle, the initiator transmits the high 32 bits address, with adding the real command code. The transaction operates identically from that particular point. To ensure compatibility having 32-bit PCI devices, it is prohibited to use a dual address cycle if it is not necessary, for example if the high-order address bits are all 0.Though the PCI bus transfers 32 bits /data (per data) phase, the initiator transmits a 4-bit byte mask mentioning which 8- bit bytes are to be considered significant. In specific, a masked write necessity affects only on the desired bytes in the target PCI device.

 

 

Posted Date: 10/13/2012 7:28:12 AM | Location : United States







Related Discussions:- Pci bus transactions - computer architecture, Assignment Help, Ask Question on Pci bus transactions - computer architecture, Get Answer, Expert's Help, Pci bus transactions - computer architecture Discussions

Write discussion on Pci bus transactions - computer architecture
Your posts are moderated
Related Questions
What are the differences between ASP and ASP .Net ?    1. ASP: Code is Interpreted ASP.NET: Code is Compiled 2. ASP: Business Logic and Presentation Logic are in a one

Q. Register-to-register operands in RISC? Register-to-register operands: In RISC machines operation which access memories are LOAD and STORE. All other operands are kept in reg

What is Read only memory (ROM) and Define the Use of it? A simple kind of ROM can be constructed from a decoder, Or gates, and a number of wires. Input

When your shell is waiting for input from the user, it should first print a prompt. The prompt should consist of the current working directory followed by the _>_ character. Here i

The final selector is connected to the (A) calling subscriber.                     (B) switching network. (C) called subscriber.                      (D) li

If you open your computers case, the motherboard is the flat, rectangular piece of circuit board to which the whole thing seems to connect to for one reason or one another. It'

Q. Changing the System Prompt? When you change the directory, you would like to keep track of it. The best way to do this is by displaying the name of the current directory alo

Write a program to find the area under the curve y = f(x) between x = a and x = b, integrate y = f(x) between the limits of a and b. The area under a curve betw   #includ

A scope resolution operator (::), can be used to describe the member functions of a class outside the class.

Q. Define Interrupts and Instruction Cycle? Let's precise the interrupt process, on the event of an interrupt, an interrupt request (in form of a signal) is concerned to CPU. T