Pci bus transactions - computer architecture, Computer Engineering

PCI bus transactions:

PCI bus traffic is prepared of a series of PCI bus transactions. Each transaction is build up of an address phase that is followed by 1 or more data phases. Direction of the data phases can be from initiator to target (write transaction) or vice-versa (read transaction), but all of the data phases ought to be in the similar direction. Either party can pause or halt the data phases at any specific point. (One common instance is a low-performance PCI device that does not support burst transactions, and always halts a transaction after the first data phase.)Any PCI device can initiate a transaction. Firstly, it might request permission from a PCI bus arbiter on the motherboard. The arbiter gives permission to 1 of the requesting devices. The initiator start the address phase by broadcasting a 32-bit address plus a 4-bit command code, then waits for an objective to respond. All other devices inspect this address and one of them responds a few cycles later.

64-bit addressing is done by using a 2-stage address phase. The initiator broadcasts the low 32 bits address, accompanied by a special "dual address cycle" command code. Components that don't support 64-bit addressing may not respond simply to that command code. In the next cycle, the initiator transmits the high 32 bits address, with adding the real command code. The transaction operates identically from that particular point. To ensure compatibility having 32-bit PCI devices, it is prohibited to use a dual address cycle if it is not necessary, for example if the high-order address bits are all 0.Though the PCI bus transfers 32 bits /data (per data) phase, the initiator transmits a 4-bit byte mask mentioning which 8- bit bytes are to be considered significant. In specific, a masked write necessity affects only on the desired bytes in the target PCI device.

 

 

Posted Date: 10/13/2012 7:28:12 AM | Location : United States







Related Discussions:- Pci bus transactions - computer architecture, Assignment Help, Ask Question on Pci bus transactions - computer architecture, Get Answer, Expert's Help, Pci bus transactions - computer architecture Discussions

Write discussion on Pci bus transactions - computer architecture
Your posts are moderated
Related Questions
When using aspx view engine, to have a steady look and feel, across all pages of the application, we can build use of asp.net master pages. What is asp.net master pages equal, when

design modulo 12 up synchronous counter using t flip flop

Advantages of Instruction set architecture: Stack Advantages : it is simple Model of expression evaluation (reverse polish). Contain Short instructions. Disadvanta

Describe the concept of pipelining. Ans: Pipelining is the means of executing machine instructions concurrently. This is the effective way of organizing concurrent activity in

What is normal form? A normal form is a guideline for relational database tables that enhances data consistency. As tables satisfy higher levels of normal forms, they are less

Define the term Electronic Cheques in briefly. The other mechanism for Internet payment is electronic cheques. Along with electronic cheques, there payer (either a business or

Problem: (a) (i) Distinguish between Complex Type and Simple Type elements. (ii) List two benefits while using XSDs in XML data modeling. (b) Both XML schema and XSL u

Q. Describe about Digital Audio Tape? The most proper tape for backing up data from a disk today is Digital Audio Tape (DAT). It employs a 4mm tape covered in a cartridge. It e


Define Grammar of a language. A formal language grammar is a set of formation rules which describe that strings formed from the alphabet of a formal language are syntactically