Pci bus transactions - computer architecture, Computer Engineering

PCI bus transactions:

PCI bus traffic is prepared of a series of PCI bus transactions. Each transaction is build up of an address phase that is followed by 1 or more data phases. Direction of the data phases can be from initiator to target (write transaction) or vice-versa (read transaction), but all of the data phases ought to be in the similar direction. Either party can pause or halt the data phases at any specific point. (One common instance is a low-performance PCI device that does not support burst transactions, and always halts a transaction after the first data phase.)Any PCI device can initiate a transaction. Firstly, it might request permission from a PCI bus arbiter on the motherboard. The arbiter gives permission to 1 of the requesting devices. The initiator start the address phase by broadcasting a 32-bit address plus a 4-bit command code, then waits for an objective to respond. All other devices inspect this address and one of them responds a few cycles later.

64-bit addressing is done by using a 2-stage address phase. The initiator broadcasts the low 32 bits address, accompanied by a special "dual address cycle" command code. Components that don't support 64-bit addressing may not respond simply to that command code. In the next cycle, the initiator transmits the high 32 bits address, with adding the real command code. The transaction operates identically from that particular point. To ensure compatibility having 32-bit PCI devices, it is prohibited to use a dual address cycle if it is not necessary, for example if the high-order address bits are all 0.Though the PCI bus transfers 32 bits /data (per data) phase, the initiator transmits a 4-bit byte mask mentioning which 8- bit bytes are to be considered significant. In specific, a masked write necessity affects only on the desired bytes in the target PCI device.

 

 

Posted Date: 10/13/2012 7:28:12 AM | Location : United States







Related Discussions:- Pci bus transactions - computer architecture, Assignment Help, Ask Question on Pci bus transactions - computer architecture, Get Answer, Expert's Help, Pci bus transactions - computer architecture Discussions

Write discussion on Pci bus transactions - computer architecture
Your posts are moderated
Related Questions
DEscribe a console application to show all the arguments passed tocommand line whereas running the application. The user can pass anynumber of arguments that should be shown. Use l

In a 10000 line exchange, 0000 to 2999 is allotted to x group of subscribers, out of which 40% are active during busy hour. The remaining numbers are domestic numbers out of which

train booking algorithm for seat reservation

Discuss different Routing plan adopted in a Telephone network. Hierarchical networks are able of handing heavy traffic where needed, and at similar time use minimal number of t

List out the main requirements between page replacement policies which should be satisfied by a page replacement policy? The major requirements that should be satisfied

Q. Explain Indirect Cycle in control unit? Once an instruction is fetched the subsequent step is to fetch the operands. The instruction may have indirect and direct addressing

Q. Explain about Synchronous DRAM? One of the most broadly used forms of DRAM is synchronous DRAM (SDRAM). Unlike the conventional DRAM that is asynchronous SDRAM exchanges dat

For executing recursive function the data structure used is: For executing recursive function, stack is used as a data structure.

What is a union ? A union, like a structure, is a derived type. Unions follow the same syntax as structures but have members that share storage. A union type defines a set of alt

Purpose: Front line client service. Make bookings for vehicle servicing, accesses client database, prints invoices for clients etc. The mechanics complete worksheets for the variou