Modes of 8254-microprocessor, Assembly Language

Assignment Help:

Modes of 8254 :

 

1632_modes of 8254.jpg

Mode 0 (Interrupt on Terminal Count)-GATE which value is 1 enables counting and GATE  which value is 0 disables counting, and GATE put not effect on OUT. The contents of the CR are transferred to CE on the first CLK pulse after CR is written into by the processor, unrelated of the signal on the GATE pin. Pulse that loads CE is not included in the count. OUT would low when there is an output to the control register and remains low till the count goes to 0.Primarily, Mode 0 is for event counting.

Mode 1 (Hardware Re -triggerabic  One-Shot)-After  CR has been loaded  with N, a 0-to-1  transition  on GATE will cause CE to be loaded, a one-to-zero transition  at OUT, and the count to start. When the count reaches to zero OUT will go high so producing a negative-going OUT pulse N clock periods long.

Mode 2 (Periodic Interval Timer)-after loading CR with N, a transfer is occur from CR to CE on the next clock pulse. OUT goes from one  to zero when the count becomes one and remains low for o1 CLK pulse; then it returns to 1 and CE is reloaded from CR, so  giving a negative pulse at OUT after each N clock cycles. GATE that value 1 enables the count and GAT that value is 0 disables the count. A 0-to-1 transition on GATE also causes the count to be reinitialized on the next clock pulse. This mode is utilized to provide a programmable periodic interval timer.

Mode 3 (Square-Wave Generator)-It is likewise to mode 2 except that OUT goes low when half the first count is reached and remains low till the count becomes zero. So the duty cycle is changed. As like before, GATE enables and disables the count and a zero to one transition on GATE reinitializes the count. This mode can be utilized for baud rate generation.

Mode 4 (Software-Triggered  Strobe)-It is likewise to mode 0 except that OUT is high while the counting is taking place and generate a one-clock-period negative pulse when the count reaches zero.

Mode 5 (Hardware-Triggered Strobe-Retriggerabic)-After CR is loaded, a O-to-I transition on GATE will cause a transfer from CR to CE during the next CLK pulse. OUT will be high in the time counting but will go low for one CLK period when the count becomes zero. GATE may reinitialize counting at any time.

For all modes, if the starting count is zero, it will be interpreted as216 or104 depending on the format of the count. The above descriptions were just to provide a whole idea of the operation of the 8254 in the several modes.

 

 


Related Discussions:- Modes of 8254-microprocessor

Digital and embedded software, hi!im looking for someone who expert in an a...

hi!im looking for someone who expert in an assembly language and help me write the programmed!Thank you

Solotuon, using 8086 assembly language that interchange upper four bits to ...

using 8086 assembly language that interchange upper four bits to lower four bits. assume that data store in byte memory and it written back to same location. and assume the data as

Login system, a pseudo-code to add username and password combination up to ...

a pseudo-code to add username and password combination up to a limit of 10

Merge Sort, Write a program to merge two sorted arrays to create a third so...

Write a program to merge two sorted arrays to create a third sorted array containing all values from the two original arrays. Merge is a key component to the mergesort algorithm.

First generation microprocessor, 1 st Generation Microprocessor : At ...

1 st Generation Microprocessor : At the end of the 70s a group of engineers developed a chip is able to processing data. This chip was called processor chip. Big processors w

Assembly language, Assembly Language: Inside the 8085, instructions ar...

Assembly Language: Inside the 8085, instructions are really stored like binary numbers, not a very good manner to look at them and very difficult to decipher. An assembler is

Program to add contents in memory-machine level programs, Example : Add th...

Example : Add the contents of the 2000H: 0500H memory location to contents of 3000H: 0600H and store the result in 5000H: 0700H. Solution : Unlike the past example progra

Interrupt priority management-microprocessor, Interrupt Priority Management...

Interrupt Priority Management The interrupt priority management logic indicated in given figure can be implemented in several ways. It does not required to be present in system

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd