8237 modes-microprocessor, Assembly Language

Assignment Help:

8237 modes :

Intel 8237 can be set to four different type of style of transfer:

1) Single - One transfer at a time,  it allow processor access to the bus between transfers.

2) Block - Transfer all data, it do not allow processor access to the bus (may cause problems with memory refresh).

3) Demand - it keep transferring as long as target keeps DRQ asserted.

4) Cascade - it allow a slave controller use of the DMAC (used for DRQ4).

 

(A) In addition, the DMA controller can be set to make continuous transfers

o   It known as auto-initialized DMA

o   normally DMA is known as "single-cycle"

 

(B) 8237 is clocked at 1/2 of ISA Bus (0.5 *BLCK)

o   up to 4.166MHz (8.33 Mhz ISA)

o   Maximum transfer rate: 4.166MB/s (16-bit DMA)

o   Maximum Programmed I/O transfer rate: 2.77 MB/s

 

(C) Size of transfer

o   Master can only produce word-sized transfers

o   Slave can produce byte-sized transfers

o   Minimum transfer size: 1 byte

o   Maximum transfer size: 64KB (8-bit),128KB (16-bit)

 


Related Discussions:- 8237 modes-microprocessor

The processor 8088-microprocessor, The processor 8088 The launching of ...

The processor 8088 The launching of the processor 8086 is consider as a remarkable step in the development of high speed computing machines. Before the introduction  of 8086 mo

Arithmetic instruction-microprocessor , Arithmetic Instruction :           ...

Arithmetic Instruction :               These instructions are usually perform the arithmetic operations, like subtraction ,multiplication, addition, and division along with th

Matrices, code to add two matrices

code to add two matrices

Second generation microprocessor, IInd Generation Microprocessor : The ...

IInd Generation Microprocessor : The second generation microprocessor by using n MOS technology seemed in the market in 1973.   The Intel  8080, of nMOS  technology

#title:Shifitng of memory, Ask 2. Exchange higher byte of AX and higher byt...

Ask 2. Exchange higher byte of AX and higher byte of BX registers by using memory location 0160 in between the transfer. Then stores AX and BX registers onto memory location 0174 o

input and output, Description: LC3 allows input from keyboard and out...

Description: LC3 allows input from keyboard and output to display on the screen. This lab will exercise the input/output capability using LC-3 Assembly language. Procedure

Multiplication using shift and add instruction, Multiply two numbers by usi...

Multiply two numbers by using shift and rotate instruction

Right triangle, code, Assembly Language How to print strings in Right Tria...

code, Assembly Language How to print strings in Right Triangle form?

Read architecture:look aside cache-microprocessor, Read Architecture : Look...

Read Architecture : Look Aside Cache In "look aside" cache architecture the main memory is located conflictingthe system interface. Both the cache main memory sees a bus cycle

Iret-loop-unconditional branch instruction-microprocessor, IRET : Return f...

IRET : Return from ISR:- When an interrupt service routine is called, before transferring control to it, the IP, CS  register and flag registers are stored in the stack to ment

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd