Memory cache hierarchy and virtual memory system, Computer Engineering

1. Detail for each of the four following MIPS instructions, which actions are being taken at each of their five steps. Do not forget to mention how and during which steps each instruction updates the program counter.

a) jalr $s0, $s1

b) sw $s1, 24($t0)

c) slt $t0, $s3, $s4

d) jal 1048576

2. Consider these two potential additions to the MIPS instruction set and explain how they would restrict pipelining.

a) cp d1(r1), d2(r2)

copy contents of word at address c address contents of r2 plus offset d2 into address contents of r1 plus displacement d2.

b) incr d2(r2)

adds one to the contents of word at address contents of r2 plus offset d2.

3. Explain how you would pipeline the four following pairs of statements.

a) add $t0, $s0, $s1

beq $s1,$s2, 300

b) add $t2, $t0, $t1

sw $t3, 36($t2)

c) add $t0, $s0, $s1

beq $t0,$s2, 300

d) lw $t0, 24($t1)

sub $s2, $t0, $t1

4. A computer system has a two-level memory cache hierarchy. The L1 cache has a zero hit penalty, a miss penalty of 5 ns and a hit rate of 95 percent. The L2 cache has a miss penalty of 100 ns and a hit rate of 90 percent.

a) How many cycles are lost for each instruction accessing the memory if the CPU clock rate is 2 GHz?

b) We can either increase the hit rate of the topmost cache to 98 percent or increase the hit rate of the second cache to 95 percent. Which improvement would have more impact?

5. A virtual memory system has a virtual address space of 4 Gigabytes and a page size of 8 Kilobytes. Each page table entry occupies 4 bytes.

a) How many bits remain unchanged during the address translation?

b) How many bits are used for the page number?

c) What is the maximum number of page table entries in a page table?

Posted Date: 3/6/2013 2:42:38 AM | Location : United States







Related Discussions:- Memory cache hierarchy and virtual memory system, Assignment Help, Ask Question on Memory cache hierarchy and virtual memory system, Get Answer, Expert's Help, Memory cache hierarchy and virtual memory system Discussions

Write discussion on Memory cache hierarchy and virtual memory system
Your posts are moderated
Related Questions
Why the temporary registers W and Z are named so I mean we start from A,B,C,D,E then H and L coz H stands for higher bit nd L for lower bit of the address pointed by memory pointer

This will be based on presentation of the report, complexity of the task, degree of completion and uniqueness of your problem.  As a part of this question, you should also inclu

What is cache memory? It is a small, fast memory that is inserted among large, slower main memory and the processor. It decreases the memory access time

Differentiate the latch and flip-flop? The major difference between latch and FF is which latches is level sensitive whereas FF is edge sensitive. They both need the use of clo

Illustrate the role of World Wide Web into the field of e-commerce. In the 1990 year, the advent of the World Wide Web upon the Internet represented a turning point into e-com

Magento is a feature-rich eCommerce platform built on open-source technology that gives online merchants with unprecedented flexibility and control over the look, content and funct

How many lines of address bus must be used to access 2048 bytes of memory when available RAM chips 128 × 8.  How many lines of these will be common to each chip? Ans. AS chips

Put the node in the right subtree Then, Put the root  Put the node in the left subtree

Accession number (bioinformatics), a unique identifier given to a biological polymer sequence (DNA, protein) when it is given to a sequence database.

design a gray to bcd code converter using 16:1 de multiplexe