Memory cache hierarchy and virtual memory system, Computer Engineering

1. Detail for each of the four following MIPS instructions, which actions are being taken at each of their five steps. Do not forget to mention how and during which steps each instruction updates the program counter.

a) jalr $s0, $s1

b) sw $s1, 24($t0)

c) slt $t0, $s3, $s4

d) jal 1048576

2. Consider these two potential additions to the MIPS instruction set and explain how they would restrict pipelining.

a) cp d1(r1), d2(r2)

copy contents of word at address c address contents of r2 plus offset d2 into address contents of r1 plus displacement d2.

b) incr d2(r2)

adds one to the contents of word at address contents of r2 plus offset d2.

3. Explain how you would pipeline the four following pairs of statements.

a) add $t0, $s0, $s1

beq $s1,$s2, 300

b) add $t2, $t0, $t1

sw $t3, 36($t2)

c) add $t0, $s0, $s1

beq $t0,$s2, 300

d) lw $t0, 24($t1)

sub $s2, $t0, $t1

4. A computer system has a two-level memory cache hierarchy. The L1 cache has a zero hit penalty, a miss penalty of 5 ns and a hit rate of 95 percent. The L2 cache has a miss penalty of 100 ns and a hit rate of 90 percent.

a) How many cycles are lost for each instruction accessing the memory if the CPU clock rate is 2 GHz?

b) We can either increase the hit rate of the topmost cache to 98 percent or increase the hit rate of the second cache to 95 percent. Which improvement would have more impact?

5. A virtual memory system has a virtual address space of 4 Gigabytes and a page size of 8 Kilobytes. Each page table entry occupies 4 bytes.

a) How many bits remain unchanged during the address translation?

b) How many bits are used for the page number?

c) What is the maximum number of page table entries in a page table?

Posted Date: 3/6/2013 2:42:38 AM | Location : United States







Related Discussions:- Memory cache hierarchy and virtual memory system, Assignment Help, Ask Question on Memory cache hierarchy and virtual memory system, Get Answer, Expert's Help, Memory cache hierarchy and virtual memory system Discussions

Write discussion on Memory cache hierarchy and virtual memory system
Your posts are moderated
Related Questions

Explain overlay structured program ? A program having overlays is termed as overlay structured program, here an overlay is a part of program that has similar load origin as som

Q. What do you mean by Decoders? Decoder transforms one kind of coded information to other form. A decoder has n inputs and one enable line (sort of selection line) and 2 n ou

Q. Explain Cell Spacing and Cell Padding? Couple of attributes known as CELLSPACING and CELLPADDING. Both are part of tag. CELLPADDING is the amount of space between

Explain the term step-wise refinement. Ans:  Step Wise Refinement  Refinement is a method of elaboration. Here one starts with a statement of function that is described a

Name the fundamental kinds of memory used in microprocessor systems There are three fundamental kinds of memory used in microprocessor systems - generallyknown asRAM, ROM, and

List the allowed register pairs of 8085. B-C register pair D-E register pair H-L register pair

Q. Explain Optimization process of Pipelining ? RISC machines can use a very efficient pipeline scheme due to the regular and simple instructions. Similarly all other instructi

Q. Describe about Physical Systems? Physical Systems are tangible entities which may be dynamic or static.   Computer Systems, Buildings,Vehicles etc. are illustrations of p

What are the components of I-way Infrastructure? There are three mechanism of the I-way infrastructure: Consumer access equipment Local on-Ramps Global informa