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Each interrupt level has a booked memory location, called an interrupt vector. All these vectors (or pointers) are stored in the interrupt table. Table lies at linear address zero, or with 64KB segments, at 0000:0000. Every vector is two words long (4 bytes). The high word has the offset and the low word the segment of the INT handler.
How INT's are Processed :
Since there are 256 levels and each vector is 4bytes long so the table contains 1024 bytes (256*4=1024). The INT number is multiplied by four to fetch the address from the table.
Whenever the CPU registers an INT it will push the FLAGS register to the stack and also push the IP and CS registers. After that the CPU deactivates the interrupt system. Then it acquires the 8-bit value the interrupting device sends and multiplies this by four to acquire the offset in the interrupt table. From this offset it acquires the address of the INT handler and carries over execution to this handler.
Usually the handler enables the interrupt system immediately to let interrupts with higher priority. Some devices also require a signal that the interrupt has been acknowledged. When the handler is stop (terminated) it might signal the 8259A PIC with an EOI (End of Interrupt). Then handler executes an IRET instruction.
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