Instruction set architecture - assembly language, Computer Engineering

Instruction Set Architecture (ISA):

The Instruction Set Architecture (ISA) is the part of the processor which is noticeable to the compiler writer or programmer. The ISA serves as the limit amongst hardware and software. We will deeply describe the instruction sets found in several of the microprocessors used today. The ISA of a processor can be explained by using 5 categories:

Operand Storage in the CPU 

  •   Where are the operands reserved other than in memory?

Number of explicit named operands 

  •   How many operands are named in a distinctive instruction?

Operand location

Can be any no. of ALU instruction operand be located in memory? Or ought to be all operands are kept internally in the CPU?

Operations

What type of operations is provided in the ISA.?

Type and size of operands

What is the size and type of per operand and how is it mention?

 In all the above the most distinctive factor is the first. The most common types of ISAs are as following:

a. Stack: - The operands are put implicitly on top of the stack.

b. Accumulator:-One operand is implicitly mentions in the accumulator.

c. General Purpose Register (GPR) - All operands are explicitly specified, they are either memory locations or registers.

Assembly code of

A = B + C;

in all  of the above three architectures:

2412_Instruction Set Architecture - assembly language.png

Notice the fact that every processor may be neatly tagged into any 1 of the above categories. The i8086 contain much instruction that use implicit operands though it has a general register set. The i8051 is another instance, it has four banks of GPRs but most instructions might have the A register as one of its operands.

 

Posted Date: 10/13/2012 3:38:00 AM | Location : United States







Related Discussions:- Instruction set architecture - assembly language, Assignment Help, Ask Question on Instruction set architecture - assembly language, Get Answer, Expert's Help, Instruction set architecture - assembly language Discussions

Write discussion on Instruction set architecture - assembly language
Your posts are moderated
Related Questions

Common channel signalling in SS7 is (A) out band control channel. (B) In band control channel. (C) Speech control channel. (D) None of the above. Ans:

Explain CMOS Inverter with the help of a neat circuit diagram. Ans: CMOS Inverter: The fundamental CMOS logic circuit is an inverter demonstrated in Fig.(a). For above

Q. What is Associative Mapping Cache? The most fastest and flexible cache organization employs an associative memory that is displayed in Figure below. The associative memory s

Often calculating all the data is not possible by aggregations for this reason some of the difficult data problems are solved. In order to verify which data should be solved and me

A distributed workstation cluster must be viewed like single computing resource and not as a group of particular workstations'.  Details of cluster were: 150MHz R4400 workstatio

What are the applications of EDI in business A.  Organistions that use EDI Extensive users of EDI contain: BHS- is a UK and European retailer dealing majorly in appare

What is the significance of the memory table 'SCREEN'? At runtime, attributes for every screen field are stored in the memory table called 'SCREEN'.  We need not declare this

State Disadvantages of object oriented analysis design You know that OO methods only create functional models within objects. There is no place in methodology to design a compl

Clocked SR flip flop A clock pulse is a sequence of logic 0, logic 1, and logic 0 occuring on the CLK input. Time t n occurs before the clock pulse and time t n+1