Explain loop level of parallel processing, Computer Engineering

Assignment Help:

Loop Level

At this stage, following loop iterations are candidates for parallel execution. Though, data dependencies among subsequent iterations can restrict parallel execution of instructions at loop level. There is vast scope for parallel execution at loop level. 

Illustration: In the subsequent loop in C language,

                        For (i=0; i <= n; i++)

                        A (i) = B (i) + C (i)

Each of the instruction A (i) =B (i) + C (i) may be implemented by different processing elements provided there are at least n processing elements. Though, the instructions in the loop

 

                        For (J=0; J<= n; J++)

                        A (J) = A (J-1) + B (J)  

Cannot be executed parallely as A (J) is data dependent on A (J-1).  It implies that before using the loop level parallelism the data dependencies should be checked.

 


Related Discussions:- Explain loop level of parallel processing

Xor gate, The XOR gate. The exclusive OR or XOR gate is similar to a tw...

The XOR gate. The exclusive OR or XOR gate is similar to a two input OR gate. The output of an XOR gate is logic 1 only when one input or the other input is high and is 0 when

Extra variables by which customers call for work to work out, What are the ...

What are the extra variables by which customers call for to work out? All customers who do not purchase Internet connectivity through a Service Provider do call for to work out

Show the spawned program, Q. Show the spawned program? include "pvm3.h"...

Q. Show the spawned program? include "pvm3.h"  main() {    int ptid, msgtag;    char buf[100];    ptid = pvm_parent();    strcpy(buf, "hello, world from ");

What is the difference between activity and sequence diagram, The following...

The following are the difference among Activity and Sequence Diagrams: A sequence diagram represents the way of processes implement in a sequence. For example, the order of op

Operation of micro controller, Consider the hardware design as shown. Withi...

Consider the hardware design as shown. Within the target system the EPROM would contain the hex data as shown below   Address  Assembly code   8000             86   8001

How to join to mwseries from power builder 8.0, Using CICS Transaction Gate...

Using CICS Transaction Gateway we can join MQ Series with Power Builder 8.0

Difference between shadow and override in programming, Overriding tell us o...

Overriding tell us only the methods, but shadowing tells us the entire element.

Minimum number of two input nand gates in assembly line, An assembly line c...

An assembly line consists of 3 fail safe sensors and one emergency shutdown switch. The line must keep moving unless any of the given conditions occur: a. When the emergency swi

Define various classes of interrupts, Q. Define Various classes of Interrup...

Q. Define Various classes of Interrupts? Figure below gives list of some common interrupts and events which causes occurrence of those interrupts. Figure: Various clas

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd