Explain loop level of parallel processing, Computer Engineering

Assignment Help:

Loop Level

At this stage, following loop iterations are candidates for parallel execution. Though, data dependencies among subsequent iterations can restrict parallel execution of instructions at loop level. There is vast scope for parallel execution at loop level. 

Illustration: In the subsequent loop in C language,

                        For (i=0; i <= n; i++)

                        A (i) = B (i) + C (i)

Each of the instruction A (i) =B (i) + C (i) may be implemented by different processing elements provided there are at least n processing elements. Though, the instructions in the loop

 

                        For (J=0; J<= n; J++)

                        A (J) = A (J-1) + B (J)  

Cannot be executed parallely as A (J) is data dependent on A (J-1).  It implies that before using the loop level parallelism the data dependencies should be checked.

 


Related Discussions:- Explain loop level of parallel processing

Example application - canonical genetic algorithm, Example Application: ...

Example Application: There are many fantastic applications of genetic algorithms. Conceivably my favorite is their usage in evaluating Jazz melodies done as part of a PhD proj

What are sequential algorithms, What are Sequential Algorithms? The cen...

What are Sequential Algorithms? The central assumption of the RAM model is that instructions are implemented one after   another, one operation at a time. Accordingly, algorith

What is selective complement - logic micro operations, SELECTIVE COMPLEMEN...

SELECTIVE COMPLEMENT The selective-complement process complements bits in register A where there are corresponding 1's inside register B. It does not affect bit positions which

Paging, specification of paging ram size is 12 frames

specification of paging ram size is 12 frames

Complex micro-controller, The 68Hc11 is actually a complex micro-controller...

The 68Hc11 is actually a complex micro-controller its contains internally RAM, EEPROM, Parallel IO and serial ports, hardware timers and a 8 channel ADC.  The internal structure is

What is the syntax of the assembler directive equ, The syntax of the assemb...

The syntax of the assembler directive EQU is ? Ans. The syntax of the assembler directive EQU is as given below: EQU

Analog-to-digital conversion process, A stationary random displacement sign...

A stationary random displacement signal was digitised at 64 samples a second and analysed to obtain an auto-spectral density.  The signal was calibrated in mm units.  The frame siz

What are different edi components and edi services, What are different EDI ...

What are different EDI components and EDI services? Different EDI components and EDI services are illustrated as: Three main components including services in EDI System are

What is sector sparing, What is sector sparing? Low-level formatting al...

What is sector sparing? Low-level formatting also sets aside spare sectors not visible to the operating system. The controller can be told to change each bad sector logically w

Java, A string S is said to be "Super ASCII", if it contains the character ...

A string S is said to be "Super ASCII", if it contains the character frequency equal to their ascii values. String will contain only lower case alphabets (''a''-''z'') and the asci

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd