Emitter bias, Electrical Engineering

Emitter bias:

596_Emitter bias.png

Figure: Emitter bias

While a split supply (dual power supply) is accessible, this biasing circuit is the very much effective, and gives zero bias voltage at the emitter or collector for load. The negative supply VEE is employed to forward-bias the emitter junction by RE. The positive supply VCC is employed to reverse-bias the collector junction. Just only two resistors are essential for the common collector stage and 4 resistors for the common emitter or common base stage.

We know that,

VB - VE = Vbe

If RB is sufficiently small, base voltage will be almost zero. Hence emitter current is,

IE = (VEE - Vbe)/RE

The operating point is independent of β if RE >> RB

Merit:

Good stability of operating point identical to voltage divider bias.

Demerit:

This type can just only be used while a split (dual) power supply is available.

Posted Date: 1/10/2013 7:28:32 AM | Location : United States







Related Discussions:- Emitter bias, Assignment Help, Ask Question on Emitter bias, Get Answer, Expert's Help, Emitter bias Discussions

Write discussion on Emitter bias
Your posts are moderated
Related Questions

What is an Opcode? The part of the instruction that specifies the operation to be performed is known as the operation code or opcode

Q. With a direct current of I A, the power expended as heat in a resistor of Ris constant, independent of time, and equal to I 2 R. Consider Problem and find in each case the effe

Determine whether the diode (considered to be ideal) in the circuit of Figure (a) is conducting.

Diagram and explanation of cro

Draw a graph illustrating how resistivity varies with temperature for an intrinsic semiconductor. b) Gallium nitride, GaN, has an energy gap of 3.36 eV at 300 K. Calculate the w

A 440-V, 60-Hz, six-pole, wye-connected, wound-rotor induction motor with a full-load speed of 1170 r/min has the following per-phase parameters referred to the stator:R 1 = R' 2

what is finger voltage?

A 3-phase transmission line is 200km long. The line has a per phase series impedance of 0.25+j0.45 Ω/km and shunt admittance of j7.2 μS/km. The line delivers 250MVA, at 0.6 lagging

The assignment comprises two parts, a CPLD Design Exercise and a CPLD Design Project. The CPLD Design Exercise will enable you to acquire competance in programmable logic design