Design a circuit using op-amp that will reject the 60kHz power line noise and also reject high signal frequency above 800Khz. The stop-band width around the 60kHz centre frequency is 10kHz. Use a cascade of 1^{st} order high pass and 1^{st} order low pass filter to implement this circuit. The voltage gain at passband frequencies is 10.
i) Explain briefly how the circuit works. Show all calculations steps and assumption made in your circuit design
ii) Show the circuit schematic with all the resistor and capacitor values labelled.
iii) Perform AC analysis on the circuit and obtain the bode diagram. The bode diagram should shows the voltage gain (Vout / Vin) in dB vs the signal frequency. Identify the -3dB cut-off frequency f_{L }and f_{H} from the plot. From the graph, estimate the roll-off rate. Based on the simulation result, comment on the performance of the filter. Does it meet the design requirement?
iv) List all components used together with its product code and price. Information on practical components should be obtained from Analog Devices, Farnell and RS website.